Datasheet
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 48 of 156
ANALOG-TO-DIGITAL CONVERSION
Each ADE5166/ADE5169/ADE5566/ADE5569 has two Σ-Δ
analog-to-digital converters (ADCs). The outputs of these ADCs
are mapped directly to waveform sampling SFRs (Address 0xE2
to Address 0xE7) and are used for energy measurement internal
digital signal processing. In PSM1 (battery) mode and PSM2
(sleep) mode, the ADCs are powered down to minimize power
consumption.
For simplicity, the block diagram in Figure 44 shows a first-order
Σ-∆ ADC. The converter is made up of the Σ-∆ modulator and
the digital low-pass filter (LPF).
A Σ-∆ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE5166/ADE5169/ADE5566/ADE5569, the sam-
pling clock is equal to 4.096 MHz/5. The 1-bit DAC in the feedback
loop is driven by the serial data stream. The DAC output is
subtracted from the input signal. If the loop gain is high enough,
the average value of the DAC output (and, therefore, the bit stream)
can approach that of the input signal level.
For any given input value in a single sampling interval, the data
from the 1-bit ADC is virtually meaningless. Only when a large
number of samples is averaged is a meaningful result obtained.
This averaging is carried into the second part of the ADC, the
digital LPF. By averaging a large number of bits from the modu-
lator, the low-pass filter can produce 24-bit data-words that are
proportional to the input signal level.
The Σ-∆ converter uses two techniques to achieve high resolution
from what is essentially a 1-bit conversion technique. The first
is oversampling. Oversampling means that the signal is sampled
at a rate (frequency) that is many times higher than the bandwidth
of interest. For example, the sampling rate in the ADE5166/
ADE5169/ADE5566/ADE5569 is 4.096 MHz/5 (819.2 kHz);
and the band of interest is 40 Hz to 2 kHz. Oversampling has
the effect of spreading the quantization noise (noise due to
sampling) over a wider bandwidth. With the noise spread more
thinly over a wider bandwidth, the quantization noise in the band
of interest is lowered (see Figure 43).
409.60 819.22
NOISE
SIGNAL
DIGITAL
FILTER
ANTIALIASING
FILTER (RC)
SAMPLING
FREQUENCY
HIGH RESOLUTION
OUTPUT FROM DIGITAL
LPF
SHAPED
NOISE
409.60 819.22
NOISE
SIGNAL
FREQUENCY (kHz)
FREQUENCY (kHz)
07411-021
Figure 43. Noise Reduction Due to Oversampling and
Noise Shaping in the Analog Modulator
However, oversampling alone is not efficient enough to improve
the signal-to-noise ratio (SNR) in the band of interest. For example,
an oversampling ratio of 4 is required to increase the SNR by only
6 dB (one bit). To keep the oversampling ratio at a reasonable level,
it is possible to shape the quantization noise so that the majority
of the noise lies at the higher frequencies. In the Σ-∆ modulator,
the noise is shaped by the integrator, which has a high-pass type of
response for the quantization noise. The result is that most of
the noise is at the higher frequencies where it can be removed
by the digital LPF. This noise shaping is shown in Figure 43.
+
–
INTEGRATOR
V
REF
1-BIT DAC
DIGITAL
LOW-PASS
FILTER
24
MCLK/5
C
R
ANALOG
LOW-PASS FILTER
... 10100101 ...
LATCHED
COMPARATOR
07411-020
Figure 44. First-Order
Σ
-∆ ADC