Datasheet

Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 137 of 156
Bit Mnemonic Default Description
[2:0] DIV2 000 Binary divider.
DIV2
Result
000 Divide by 1 (see Table 149)
001 Divide by 2 (see Table 149)
010 Divide by 4 (see Table 149)
011 Divide by 8 (see Table 149)
100 Divide by 16 (see Table 149)
101 Divide by 32 (see Table 149)
110 Divide by 164 (see Table 149)
111
Divide by 128 (see Table 149)
Table 149. Common Baud Rates Using the UART2 Timer with a 4.096 MHz PLL Clock
Ideal Baud CD SBTH2 DIV2 SBF2 % Error
115,200 0 0 1 0 +0.16
115,200 1 0 0 0 +0.16
57,600
0
0
2
0
+0.16
57,600 1 0 1 0 +0.16
38,400
0
0
2
1
−0.31
38,400
1
0
1
1
−0.31
38,400 2 0 0 1 −0.31
19,200 0 0 3 1 −0.31
19,200 1 0 2 1 −0.31
19,200 2 0 1 1 −0.31
19,200 3 0 0 1 −0.31
9600 0 0 4 1 −0.31
9600 1 0 3 1 −0.31
9600 2 0 2 1 −0.31
9600 3 0 1 1 −0.31
9600
4
0
0
1
−0.31
4800 0 0 5 1 −0.31
4800 1 0 4 1 −0.31
4800 2 0 3 1 −0.31
4800 3 0 2 1 −0.31
4800 4 0 1 1 −0.31
4800 5 0 0 1 −0.31
2400
0
0
6
1
−0.31
2400 1 0 5 1 −0.31
2400 2 0 4 1 −0.31
2400 3 0 3 1 −0.31
2400 4 0 2 1 −0.31
2400
5
0
1
1
−0.31
2400 6 0 0 1 −0.31
300 0 2 7 1 −0.31
300 1 1 7 1 −0.31
300 2 0 7 1 −0.31
300 3 0 6 1 −0.31
300 4 0 5 1 −0.31
300 5 0 4 1 −0.31
300 6 0 3 1 −0.31
300 7 0 2 1 −0.31