Datasheet
REV. B
–6–
ADDAC80/ADDAC85/ADDAC87–SPECIFICATIONS
ADDAC85LD ADDAC85MIL ADDAC87
Model Min Typ Max Min Typ Max Min Typ Max Unit
POWER SUPPLY REQUIREMENTS
Rated Voltages ±15, 5 ±15, 5 ±15, 5 V
Range
Analog Supplies ±14.5 ±15.5 ±14.5 ±15.5 ±13.5 ±16.5 V
Logic Supplies +4.5 ±15.5 +4.5 +15.5 +4.5 ±16.5 V
Supply Drain
7
+15 V 15 20 15 20 10 20 mA
–15 V 25 30 25 30 20 35 mA
+5 V
8
15 20 15 20 10 20 mA
TEMPERATURE RANGE
Specification –25 +85 –55 +125 –55 +125 °C
Operating –55 +125 –55 +125 –55 +125 °C
Storage –55 +125 –55 +125 –65 +150 °
C
NOTES
1
Least Significant Bit.
2
Adjustable to zero with external trim potentiometer.
3
FSR means “Full-Scale Range” and is 20 V for the ± 10 V range and 10 V for the ±5 V range.
4
Gain and offset errors adjusted to zero at 25°C.
5
C
F
= 0, see Figure 3a.
6
Maximum with no degradation of specification, must be a constant load.
7
Including 5 mA load.
8
5 V supply required only for CCD versions.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
+V
S
to Power Ground . . . . . . . . . . . . . . . . . . . . 0 V to +18 V
–V
S
to Power Ground . . . . . . . . . . . . . . . . . . . . 0 V to –18 V
Digital Inputs (Pins 1 to 12) to Power Ground . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.0 V to +7 V
Ref In to Reference Ground . . . . . . . . . . . . . . . . . . . . . ±12 V
Bipolar Offset to Reference Ground . . . . . . . . . . . . . . ±12 V
10 V Span R to Reference Ground . . . . . . . . . . . . . . . ±12 V
20 V Span R to Reference Ground . . . . . . . . . . . . . . . ±24 V
Ref Out . . . . . . . . . Indefinite Short to Power Ground or +V
S
*NC = CBI VERSIONS
5V – CCD VERSIONS
(MSB) BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
(LSB) BIT 12
V
REF
OUT
GAIN ADJUST
+V
S
COMMON
SUMMING JUNCTION
20V RANGE
10V RANGE
BIPOLAR OFFSET
REF INPUT
V
OUT
–V
S
NC/+V
L
*
12-BIT
RESISTOR
LADDER
NETWORK
AND
CURRENT
SWITCHES
REF
CONTROL
CIRCUIT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
6.3k
5k
5k
ADDAC80
+
–
Figure 1. Voltage Model Function Diagram
and Pin Configuration
*NC = CBI VERSIONS
5V – CCD VERSIONS
(MSB) BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
(LSB) BIT 12
V
REF
OUT
GAIN ADJUST
+V
S
COMMON
SCALING NETWORK
SCALING NETWORK
SCALING NETWORK
BIPOLAR OFFSET
REF INPUT
I
OUT
–V
S
NC/+V
L
*
12-BIT
RESISTOR
LADDER
NETWORK
AND
CURRENT
SWITCHES
REF
CONTROL
CIRCUIT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
6.3k
2k
5k
5k
Figure 2. Current Model Functional Diagram
and Pin Configuration
(continued)