Datasheet

ADCLK948
Rev. A | Page 6 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. NC = NO CONNECT.
2
. EPAD MUST BE SOLDERED TO
V
EE
POWER PLANE.
PIN 1
INDICATOR
1CLK0
2CLK0
3
V
REF
0
4V
T
0
5CLK1
6CLK1
7V
T
1
8
V
REF
1
24 Q2
23 Q2
22 Q3
21 Q3
20 Q4
19 Q4
18 Q5
17 Q5
9
N
C
10
V
CC
11
Q7
12
Q7
13
Q6
14
Q6
15
V
CC
16
V
CC
32
IN_SEL
31
V
CC
30
Q0
29
Q0
28
Q1
27
Q1
26
V
CC
25
V
CC
TOP VIEW
(Not to Scale)
ADCLK948
0
8280-002
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1 CLK0 Differential Input (Positive) 0.
2
CLK0
Differential Input (Negative) 0.
3 V
REF
0
Reference Voltage. Reference voltage for biasing ac-coupled CLK0 and CLK0
inputs.
4 V
T
0
Center Tap. Center tap of a 100 Ω input resistor for CLK0 and CLK0
inputs.
5 CLK1 Differential Input (Positive) 1.
6
CLK1
Differential Input (Negative) 1.
7 V
T
1
Center Tap. Center tap of a 100 Ω input resistor for CLK1 and CLK1
inputs.
8 V
REF
1
Reference Voltage. Reference voltage for biasing ac-coupled CLK1 and CLK1
inputs.
9 NC No Connection.
10, 15, 16, 25, 26, 31 V
CC
Positive Supply Pin.
11, 12
Q7
, Q7
Differential LVPECL Outputs.
13, 14
Q6
, Q6
Differential LVPECL Outputs.
17, 18
Q5
, Q5
Differential LVPECL Outputs.
19, 20
Q4
, Q4
Differential LVPECL Outputs.
21, 22
Q3
, Q3
Differential LVPECL Outputs.
23, 24
Q2
, Q2
Differential LVPECL Outputs.
27, 28
Q1
, Q1
Differential LVPECL Outputs.
29, 30
Q0
, Q0
Differential LVPECL Outputs.
32 IN_SEL
Input Select. Logic 0 selects CLK0 and CLK0
inputs. Logic 1 selects CLK1 and CLK1 inputs.
EPAD The exposed pad (EPAD) must be connected to V
EE
.