Datasheet

ADCLK944
Rev. 0 | Page 3 of 12
SPECIFICATIONS
Typical values are given for V
CC
− V
EE
= 3.3 V and T
A
= 25°C, unless otherwise noted. Minimum and maximum values are given for the
full V
CC
− V
EE
= 3.3 V + 10% to 2.5 V − 5% and T
A
= −40°C to +85°C variation, unless otherwise noted.
CLOCK INPUTS AND OUTPUTS
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC INPUT CHARACTERISTICS
Input Common-Mode Voltage V
ICM
V
EE
+ 1.35 V
CC
− 0.1 V
Input Differential Voltage V
ID
0.4 3.4 V p-p ±1.7 V between input pins
Input Capacitance C
IN
0.4 pF
Input Resistance R
IN
Single-Ended Mode 50 Ω
Differential Mode 100 Ω
Common Mode 50 kΩ V
T
open
Input Bias Current 20 μA
DC OUTPUT CHARACTERISTICS
Output Voltage High Level V
OH
V
CC
− 1.26 V
CC
− 0.76 V Load = 50 Ω to (V
CC
− 2.0 V)
Output Voltage Low Level V
OL
V
CC
− 1.99 V
CC
− 1.54 V Load = 50 Ω to (V
CC
− 2.0 V)
Output Voltage, Single-Ended V
O
600 960 mV V
OH
− V
OL
, output static
Voltage Reference V
REF
Output Voltage (V
CC
+ 1)/2 V −500 μA to +500 μA
Output Resistance 250 Ω
TIMING CHARACTERISTICS
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
AC PERFORMANCE
Maximum Output Frequency 6.2 7.0 GHz
Differential output voltage swing > 0.8 V
(see Figure 4)
Output Rise/Fall Time t
R
35 50 75 ps 20% to 80%, measured differentially
Propagation Delay t
PD
70 100 130 ps V
ID
= 1.6 V p-p
Temperature Coefficient 75 fs/°C
Output-to-Output Skew
1
15 ps
Part-to-Part Skew 35 ps V
ID
= 1.6 V p-p
Additive Time Jitter
Integrated Random Jitter 26 fs rms BW = 12 kHz to 20 MHz, CLK = 1 GHz
Broadband Random Jitter
2
50 fs rms V
ID
= 1.6 V p-p, 8 V/ns, V
ICM
= 2 V
CLOCK OUTPUT PHASE NOISE
Absolute Phase Noise Input slew rate > 1 V/ns (see Figure 11)
f
IN
= 1 GHz −118 dBc/Hz 100 Hz offset
−135 dBc/Hz 1 kHz offset
−144 dBc/Hz 10 kHz offset
−150 dBc/Hz 100 kHz offset
−150 dBc/Hz >1 MHz offset
1
The output-to-output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
2
Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method.