Datasheet

ADCLK854
Rev. 0 | Page 13 of 16
CONTROL AND FUNCTION PINS
CTRL_A—Logic Select
This pin selects either CMOS (high) or LVDS (low) logic for
Output 3, Output 2, Output 1, and Output 0. This pin has an
internal 200 kΩ pull-down resistor.
CTRL_B—Logic Select
This pin selects either CMOS (high) or LVDS (low) logic for
Output 7, Output 6, Output 5, and Output 4. This pin has an
internal 200 kΩ pull-down resistor.
CTRL_C—Logic Select
This pin selects either CMOS (high) or LVDS (low) logic for
Output 11, Output 10, Output 9, and Output 8. This pin has an
internal 200 kΩ pull-down resistor.
IN_SEL—Clock Input Select
A logic low selects CLK0 and
CLK0
whereas a logic high selects
CLK1 and
CLK1
. This pin has an internal 200 kΩ pull-down
resistor.
Sleep Mode
Sleep mode powers down the chip except for the internal band
gap. The input is active high, which puts the outputs into a
high-Z state. This pin has a 200 kΩ pull-down resistor.
POWER SUPPLY
The ADCLK854 requires a 1.8 V ± 5% power supply for V
S
. Best
practice recommends bypassing the power supply on the PCB
with adequate capacitance (>10 μF), and bypassing all power
pins with adequate capacitance (0.1 μF) as close to the part as
possible. The layout of the ADCLK854 evaluation board
(ADCLK854/PCBZ) provides a good layout example.
Exposed Metal Paddle
The exposed metal paddle on the ADCLK854 package is an
electrical connection as well as a thermal enhancement. For the
device to function properly, the paddle must be properly
attached to ground (GND). The ADCLK854 dissipates heat
through its exposed paddle. The PCB acts as a heat sink for the
ADCLK854. The PCB attachment must provide a good thermal
path to a larger heat dissipation area, such as the ground plane
on the PCB. This requires a grid of vias from the top layer down
to the ground plane. See Figure 23 for an example.
VIAS TO GND PLANE
07218-023
Figure 23. PCB Land for Attaching Exposed Paddle