Datasheet

ADCLK846
Rev. B | Page 5 of 16
CLOCK CHARACTERISTICS
Table 3. Clock Output Phase Noise
Parameter Min Typ Max Unit Conditions
CLK-TO-LVDS ABSOLUTE PHASE NOISE Input slew rate > 1 V/ns
1000 MHz −90 dBc/Hz At 10 Hz offset
−108 dBc/Hz At 100 Hz offset
−117 dBc/Hz At 1 kHz offset
−126 dBc/Hz At 10 kHz offset
−134 dBc/Hz At 100 kHz offset
−141 dBc/Hz At 1 MHz offset
−146 dBc/Hz At 10 MHz offset
CLK-TO-CMOS ABSOLUTE PHASE NOISE Input slew rate > 1 V/ns
200 MHz −100 dBc/Hz At 10 Hz offset
−117 dBc/Hz At 100 Hz offset
−128 dBc/Hz At 1 kHz offset
−138 dBc/Hz At 10 kHz offset
−147 dBc/Hz At 100 kHz offset
−153 dBc/Hz At 1 MHz offset
−156 dBc/Hz At 10 MHz offset
LOGIC AND POWER CHARACTERISTICS
Table 4. Control Pin Characteristics
Parameter Symbol Min Typ Max Unit Conditions
CONTROL PINS
(CTRL_A, CTRL_B, SLEEP)
1
Logic 1 Voltage V
IH
V
S
− 0.4 V
Logic 0 Voltage V
IL
0.4 V
Logic 1 Current I
IH
5 8 20 A
Logic 0 Current I
IL
−5 +5 A
Capacitance 2 pF
POWER
Supply Voltage Requirement V
S
1.71 1.8 1.89 V V
S
= 1.8 V ± 5%
LVDS Outputs, Full Operation
LVDS at 100 MHz 55 70 mA All outputs enabled as LVDS and loaded, R
L
= 100 Ω
LVDS at 1200 MHz 110 130 mA All outputs enabled as LVDS and loaded, R
L
= 100 Ω
CMOS Outputs, Full Operation
CMOS at 100 MHz 75 95 mA
All outputs enabled as CMOS and loaded,
CMOS load = 10 pF
CMOS at 250 MHz 155 190 mA
All outputs enabled as CMOS and loaded,
CMOS load = 10 pF
Sleep 3 mA
SLEEP pin pulled high; does not include power
dissipated in external resistors
Power Supply Rejection
2
LVDS PSR
TPD
0.9 ps/mV
CMOS PSR
TPD
1.2 ps/mV
1
These pins each have a 200 kΩ internal pull-down resistor.
2
Change in T
PD
per change in V
S
.