Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsADAV803ASTZ

Audio Codec for Recordable DVD

ADAV803

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Stereo analog-to-digital converter (ADC)

Supports 48 kHz/96 kHz sample rates

102 dB dynamic range

Single-ended input

Automatic level control

Stereo digital-to-analog converter (DAC)

Supports 32 kHz/44.1 kHz/48 kHz/96 kHz/192 kHz

sample rates

101 dB dynamic range

Single-ended output

Asynchronous operation of ADC and DAC

Stereo sample rate converter (SRC)

Input/output range: 8 kHz to 192 kHz

140 dB dynamic range

Digital interfaces

Record

Playback

Auxiliary record

Auxiliary playback

S/PDIF (IEC 60958) input and output

Digital interface receiver (DIR)

Digital interface transmitter (DIT)

PLL-based audio MCLK generators

Generates required DVDR system MCLKs

Device control via I

C-compatible serial port

64-lead LQFP package

FUNCTIONAL BLOCK DIAGRAM

ANALOG-TO-DIGITAL

CONVERTER

REFERENCE SRC

DIGITAL-TO-ANALOG

CONVERTER

ADAV803

DIT

AUX DATA

OUTPUT

RECORD

DATA

OUTPUT

CONTROL

REGISTERS

PLL

DIGITAL

INPUT/OUTPUT

SWITCHING MATRIX

(DATA PATH)

PLAYBACK

DATA INPUT

AUX DATA

INPUT

DIR

VINL

VINR

VREF

VOUTR

FILTD

IAUXLRCLK

IAUXBCLK

IAUXSDATA

DIRIN

OLRCLK

OBCLK

OSDATA

OAUXLRCLK

OAUXBCLK

OAUXSDATA

DITOUT

SDA

SCL

AD0

AD1

SYSCLK3

SYSCLK2

SYSCLK1

ZEROL/INT

ZEROR

MCLKI

XOUT

XIN

MCLKO

VOUTL

04756-001

ILRCLK

IBCLK

ISDATA

Figure 1.

APPLICATIONS

DVD-recordable

All formats

CD-R/W

GENERAL DESCRIPTION

The ADAV803 is a stereo audio codec intended for applications

such as DVD or CD recorders that require high performance

and flexible, cost-effective playback and record functionality.

The ADAV803 features Analog Devices, Inc. proprietary, high

performance converter cores to provide record (ADC),

playback (DAC), and format conversion (SRC) on a single chip.

The ADAV803 record channel features variable input gain to

allow for adjustment of recorded input levels and automatic

level control, followed by a high performance stereo ADC

whose digital output is sent to the record interface. The record

channel also features level detectors that can be used in

feedback loops to adjust input levels for optimum recording.

The playback channel features a high performance stereo DAC

with independent digital volume control.

The sample rate converter (SRC) provides high performance

sample rate conversion to allow inputs and outputs that require

different sample rates to be matched. The SRC input can be

selected from playback, auxiliary, DIR, or ADC (record). The

SRC output can be applied to the playback DAC, both main and

auxiliary record channels, and a DIT. Operation of the ADAV803

is controlled via an I

C®-compatible serial interface, which

allows the programming of individual control register settings.

The ADAV803 operates from a single analog 3.3 V power

supply and a digital power supply of 3.3 V with an optional

digital interface range of 3.0 V to 3.6 V.

The part is housed in a 64-lead LQFP package and is character-

ized for operation over the commercial temperature range of

−40°C to +85°C.

Summary of content (60 pages)

PAGE 1
Audio Codec for Recordable DVD ADAV803 PLL VINL VINR ANALOG-TO-DIGITAL CONVERTER VREF REFERENCE VOUTL VOUTR AD1 AD0 SCL SDA SYSCLK3 SYSCLK2 SYSCLK1 MCLKO MCLKI FUNCTIONAL BLOCK DIAGRAM XOUT CONTROL REGISTERS RECORD DATA OUTPUT DIGITAL INPUT/OUTPUT SWITCHING MATRIX (DATA PATH) SRC DIGITAL-TO-ANALOG CONVERTER AUX DATA OUTPUT DIT OLRCLK OBCLK OSDATA OAUXLRCLK OAUXBCLK OAUXSDATA DITOUT FILTD ZEROL/INT ZEROR Figure 1.
PAGE 2
ADAV803 TABLE OF CONTENTS Features .............................................................................................. 1 DAC Section................................................................................ 18 Functional Block Diagram .............................................................. 1 Sample Rate Converter (SRC) Functional Overview ............ 19 Applications....................................................................................... 1 PLL Section ............
PAGE 3
ADAV803 SPECIFICATIONS TEST CONDITIONS Test conditions, unless otherwise noted. Table 1. Test Parameter Supply Voltage Analog Digital Ambient Temperature Master Clock (MCLKI) Measurement Bandwidth Word Width (All Converters) Load Capacitance on Digital Outputs ADC Input Frequency DAC Output Frequency Digital Input Digital Output Condition 3.3 V 3.3 V 25°C 12.288 MHz 20 Hz to 20 kHz 24 bits 100 pF 1007.8125 Hz at −1 dBFS 960.
PAGE 4
ADAV803 Parameter Crosstalk (EIAJ Method) Volume Control Step Size (256 Steps) Maximum Volume Attenuation Mute Attenuation Group Delay fS = 48 kHz fS = 96 kHz ADC LOW-PASS DIGITAL DECIMATION FILTER CHARACTERISTICS 1 Pass-Band Frequency Min Typ −110 0.39 −48 ∞ Stop-Band Frequency Stop-Band Attenuation Pass-Band Ripple ADC HIGH-PASS DIGITAL FILTER CHARACTERISTICS Cutoff Frequency SRC SECTION Resolution Sample Rate SRC MCLK Max Unit dB % per step dB dB μs μs 22 44 26 52 120 120 ±0.01 ±0.
PAGE 5
ADAV803 Parameter Crosstalk (EIAJ Method) Phase Deviation Mute Attenuation Volume Control Step Size (256 Steps) Group Delay 48 kHz 96 kHz 192 kHz DAC LOW-PASS DIGITAL INTERPOLATION FILTER CHARACTERISTICS Pass-Band Frequency Min Stop-Band Frequency Stop-Band Attenuation Pass-Band Ripple PLL SECTION Master Clock Input Frequency Generated System Clocks MCLKO SYSCLK1 SYSCLK2 SYSCLK3 Jitter SYSCLK1 SYSCLK2 SYSCLK3 DIR SECTION Input Sample Frequency Differential Input Voltage DIT SECTION Output Sample Freque
PAGE 6
ADAV803 Parameter POWER Supplies Voltage, AVDD Voltage, DVDD Voltage, ODVDD Operating Current Analog Current Digital Current Digital Interface Current DIRIN/DIROUT Current PLL Current Power-Down Current Analog Current Digital Current Digital Interface Current DIRIN/DIROUT Current PLL Current Power Supply Rejection Signal at Analog Supply Pins 1 Min Typ Max Unit 3.0 3.0 3.0 3.3 3.3 3.3 3.6 3.6 3.6 V V V 60 38 13 mA mA mA mA mA Comments All supplies at 3.3 V 5 18 RESET low, no MCLK 18 2.
PAGE 7
ADAV803 TIMING SPECIFICATIONS Timing specifications are guaranteed over the full temperature and supply range. Table 3. Parameter MASTER CLOCK AND RESET MCLKI Frequency XIN Frequency RESET Low Symbol Min fMCLK fXIN tRESET 20 fSCL tSCLH tSCLL 0.6 1.3 Typ Max Unit 12.
PAGE 8
ADAV803 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter DVDD to DGND and ODVDD to DGND AVDD to AGND Digital Inputs Analog Inputs AGND to DGND Reference Voltage Soldering (10 sec) Rating 0 V to 4.6 V 0 V to 4.6 V DGND − 0.3 V to DVDD + 0.3 V AGND − 0.3 V to AVDD + 0.3 V −0.3 V to +0.3 V Indefinite short circuit to ground 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 9
ADAV803 VOUTR NC VOUTL NC AVDD AGND FILTD AGND VREF AGND AVDD CAPRN CAPRP AGND CAPLP CAPLN PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VINR 48 ADVDD 47 ADGND AGND 3 46 PLL_LF2 AVDD 4 45 PLL_LF1 DIR_LF 5 44 PLL_GND DIR_GND 6 43 PLL_VDD DIR_VDD 7 42 DGND 41 SYSCLK1 40 SYSCLK2 39 SYSCLK3 SCL 11 38 XIN AD1 12 37 XOUT ZEROL/INT 13 36 MCLKO ZEROR 14 35 MCLKI DVDD 15 34 DVDD DGND 16 33 DGND 1 VINL 2 PIN 1
PAGE 10
ADAV803 Pin No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Mnemonic OAUXLRCLK OAUXBCLK OAUXSDATA IAUXLRCLK IAUXBCLK IAUXSDATA DGND DVDD MCLKI MCLKO XOUT XIN SYSCLK3 SYSCLK2 SYSCLK1 DGND PLL_VDD PLL_GND PLL_LF1 PLL_LF2 ADGND ADVDD VOUTR NC VOUTL NC AVDD AGND FILTD AGND VREF AGND AVDD CAPRN CAPRP AGND CAPLP CAPLN I/O I/O I/O O I/O I/O I I O I I O O O O O Description Sampling Clock (LRCLK) of Auxiliary Digital Output Port.
PAGE 11
ADAV803 TYPICAL PERFORMANCE CHARACTERISTICS –50 –100 –150 0 0.5 1.0 1.5 FREQUENCY (Normalized to fS) –50 –100 –150 2.0 04756-006 MAGNITUDE (dB) 0 04756-003 MAGNITUDE (dB) 0 0 Figure 3. ADC Composite Filter Response 96 192 FREQUENCY (kHz) 288 384 Figure 6. DAC Composite Filter Response, 48 kHz 5 0 0 –10 –15 –20 –30 04756-004 –25 0 5 10 FREQUENCY (Hz) 15 –50 –100 –150 20 04756-007 MAGNITUDE (dB) MAGNITUDE (dB) –5 0 24 FREQUENCY (kHz) 36 48 Figure 7.
PAGE 12
ADAV803 0 0 MAGNITUDE (dB) MAGNITUDE (dB) –50 –50 –100 –100 0 192 384 FREQUENCY (kHz) 576 –200 768 Figure 9. DAC Composite Filter Response, 96 kHz 04756-012 –150 04756-009 –150 0 384 768 FREQUENCY (kHz) 1152 1536 Figure 12. DAC Composite Filter Response, 192 kHz 0 0 MAGNITUDE (dB) MAGNITUDE (dB) –2 –50 –100 –4 –6 0 24 48 FREQUENCY (kHz) 72 04756-013 –150 04756-010 –8 –10 48 96 Figure 10. DAC Pass-Band Filter Response, 96 kHz 64 80 FREQUENCY (kHz) 96 Figure 13.
PAGE 13
ADAV803 0 0 DNR = 102dB (A-WEIGHTED) –20 THD+N = 95dB –20 –60 –80 –100 –60 –80 –100 –120 –120 –140 –140 –160 0 2 4 6 8 10 12 14 FREQUENCY (kHz) 16 18 –160 20 04756-018 MAGNITUDE (dB) –40 04756-015 MAGNITUDE (dB) –40 0 Figure 15.
PAGE 14
ADAV803 0 0 DNR = 102dB (A-WEIGHTED) –20 –60 –80 –100 –60 –80 –100 –120 –120 –140 –140 0 8 16 24 32 FREQUENCY (kHz) 40 48 Figure 21. ADC Dynamic Range, fS = 96 kHz –160 04756-022 MAGNITUDE (dB) –40 04756-021 MAGNITUDE (dB) –40 –160 THD+N = 92dB (VIN = –3dB) –20 0 8 16 24 32 FREQUENCY (kHz) Figure 22. ADC THD + N, fS = 96 kHz Rev.
PAGE 15
ADAV803 FUNCTIONAL DESCRIPTION ADC SECTION Programmable Gain Amplifier (PGA) The ADAV803’s ADC section is implemented using a secondorder multibit (5 bits) Σ-Δ modulator. The modulator is sampled at either half of the ADC MCLK rate (modulator clock = 128 × fS) or one-quarter of the ADC MCLK rate (modulator clock = 64 × fS). The digital decimator consists of a Sinc^5 filter followed by a cascade of three half-band FIR filters. The Sinc decimates by a factor of 16 at 48 kHz and by a factor of 8 at 96 kHz.
PAGE 16
ADAV803 Automatic Level Control (ALC) No Recovery Mode The ADC record channel features a programmable automatic level control block. This block monitors the level of the ADC output signal and automatically reduces the gain, if the signal at the input pins causes the ADC output to exceed a preset limit. This function can be useful to maximize the signal dynamic range when the input level is not well defined.
PAGE 17
ADAV803 Selecting a Sample Rate selecting the lower modulator rate reduces the amount of digital noise, improving THD + N, but also reduces the oversampling ratio, therefore reducing the dynamic range by a corresponding amount. The output sample rate of the ADC is always ADC MCLK/256, as shown in Figure 23. By default, the ADC modulator runs at ADC MCLK/2. When the ADC MCLK exceeds 12.288 MHz, the ADC modulator should be set to run at ADC MCLK/4.
PAGE 18
ADAV803 DAC SECTION Selecting a Sample Rate The ADAV803 has two DAC channels arranged as a stereo pair with single-ended analog outputs. Each channel has its own independently programmable attenuator, adjustable in 128 steps of 0.375 dB per step. The DAC can receive data from the playback or auxiliary input ports, the SRC, the ADC, or the DIR. Each analog output pin sits at a dc level of VREF, and swings 1.0 V rms for a 0 dB digital input signal.
PAGE 19
ADAV803 The frequency domain shows the wide side lobes that result from this error when the sampling of fS_OUT is convolved with the attenuated images from the sin(x)/x nature of the zero-order hold. The images at fS_IN (dc signal images) of the zero-order hold are infinitely attenuated. Because the ratio of T2 to T1 is an irrational number, the error resulting from the resampling at fS_OUT can never be eliminated.
PAGE 20
ADAV803 The worst-case images can be computed from the zero-order hold frequency response: Maximum Image = sin(π × F/fS_INTERP)/(π × F/fS_INTERP) This technique is supported by the Fourier transform property that, if f(t) is F(ω), then f(k × t) is F(ω/k). Thus, the range of decimation is limited by the size of the RAM. SRC Architecture The following worst-case images would appear for fS_IN equal to 192 kHz: Image at fS_INTERP − 96 kHz = −125.1 dB Image at fS_INTERP + 96 kHz = −125.
PAGE 21
ADAV803 write address pointer is useful for applications in which small changes in the sample rate ratio between fS_IN and fS_OUT are expected. The maximum decimation rate can be calculated from the RAM word depth and the group delay as (512 − 16)/64 taps = 7.75 for short group delay and (512 − 64)/64 taps = 7 for long group delay.
PAGE 22
ADAV803 Table 7. PLL Frequency Selection Options The ADAV803 features a dual PLL configuration to generate independent system clocks for asynchronous operation. Figure 37 shows the block diagram of the PLL section. The PLL generates the internal and system clocks from a 27 MHz clock. This clock is generated either by a crystal connected between XIN and XOUT, as shown in Figure 35, or from an external clock source connected directly to XIN.
PAGE 23
ADAV803 PLL1 MCLK PLL2 MCLK REG 0x75 BITS[3:2] PLL1 REG 0x75 BIT 0 ×2 FS1 256 384 ÷2 ×2 FS2 ÷2 REG 0x74 BIT 0 256 512 SYSCLK2 REG 0x77 BITS[2:1] REG 0x75 BITS[7:6] 48kHz 32kHz 44.1kHz PLLINT1 PLL2 REG 0x75 BIT 4 REG 0x75 BIT 5 256 384 SYSCLK1 REG 0x77 BIT 0 REG 0x75 BIT 1 FS3 ÷2 PLLINT2 SYSCLK3 04756-038 48kHz 32kHz 44.1kHz Figure 38. PLL Clocking Scheme DIR 04756-040 REG 0x63 BITS[2:0] Figure 40.
PAGE 24
ADAV803 The ADAV803 can receive and transmit S/PDIF, AES/EBU, and IEC-958 serial streams. S/PDIF is a consumer audio standard, and AES/EBU is a professional audio standard. IEC-958 has both consumer and professional definitions. This data sheet is not intended to fully define or to provide a tutorial for these standards. Contact the international standards-setting bodies for the full specifications.
PAGE 25
ADAV803 Address1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19 N + 20 N + 21 N + 22 N + 23 6 5 Lock 4 Data Bits 3 2 Emphasis 1 0 Sample NonPro/Con Frequency Audio = 1 User Bit Management Channel Mode Alignment Source Word Use of Auxiliary Mode Level Length Sample Bits Channel Identification Reserved Digital Audio fS Sample Scaling Frequency (fS) Reference Signal Reserved Alphanumeric Channel Origin Data—First Character Alphanumeric Channel
PAGE 26
ADAV803 The size of the user bit buffer can be set by programming the RxBCONF0 bit in the receiver buffer configuration register, as shown in Table 11. bit is set. This is a sticky bit that remains high until the register is read. Table 11. RxBCONF3 Functionality The S/PDIF transmitter has a similar buffer structure to the receive section. The transmitter channel status buffer occupies 24 bytes of the register map.
PAGE 27
ADAV803 Table 15. Transmitter User Bit Buffer Size TxBCONF0 0 1 Buffer Size 384 bits with Preamble Z as the start of the block. 768 bits with Preamble Z as the start of the block. By using sticky bits and interrupts, the transmit buffers can notify the host or microcontroller about their status. The sticky bit, TxUBINT, is set when the transmit user bit buffer has been updated and the second transmit user bit buffer is empty and ready to accept new user bits.
PAGE 28
ADAV803 REG 0x76 BITS[4:2] DIR PLL(512 × fS) DIR PLL(256 × fS) PLLINT1 PLLINT2 MCLKI XIN ADC OUTPUT PORT MCLK ICLK1 ICLK2 PLL CLOCK REG 0x76 BITS[7:5] DIR PLL(512 × fS) DIR PLL(256 × fS) PLLINT1 PLLINT2 MCLKI XIN Care should be taken to ensure that the clock rate is appropriate for whatever block is connected to the serial port.
PAGE 29
ADAV803 OSCILLATOR PLL The ADAV803 features a digital input/output switching/ multiplexing matrix that gives flexibility to the range of possible input and output connections. Digital input ports include playback and auxiliary input (both 3-wire digital), and S/PDIF (single-wire to the on-chip receiver). Output ports include the record and auxiliary output ports (both 3-wire digital) and the S/PDIF port (single-wire from the on-chip transmitter).
PAGE 30
ADAV803 INTERFACE CONTROL The ADAV803 has a dedicated control port to allow the internal registers of the ADAV803 to be accessed. Each of the internal registers is eight bits wide. Where bits are described as reserved (RES), these bits should be programmed as zero. Initiating a write operation to the ADAV803 involves sending a start condition and then sending the device address with the R/W set low. The ADAV803 responds by issuing an ACK to indicate that it has been addressed.
PAGE 31
ADAV803 SCL SDA 0 0 START BY MASTER 1 0 0 AD1 AD0 R/W 1 1 ACK. BY ADAV803 FRAME 1 CHIP ADDRESS BYTE 0 1 0 0 0 X ACK. BY ADAV803 FRAME 2 REGISTER ADDRESS BYTE SCL (CONTINUED) 0 0 REPEATED START BY MASTER 1 0 0 AD1 AD0 R/W D7 ACK. BY ADAV803 FRAME 3 CHIP ADDRESS BYTE D6 D5 D4 D3 D2 FRAME 4 REGISTER DATA D1 D0 ACK. BY ADAV803 STOP BY MASTER 04756-054 SDA (CONTINUED) Figure 54.
PAGE 32
ADAV803 REGISTER DESCRIPTIONS SRC and Clock Control—Address 0000000 (0x00) Table 17. SRC and Clock Control Register Bit Map 7 SRCDIV1 6 SRCDIV0 5 CLK2DIV1 4 CLK2DIV0 3 CLK1DIV1 2 CLK1DIV0 1 MCLKSEL1 0 MCLKSEL0 3 Reserved 2 Reserved 1 Reserved 0 TxMUX Table 18. SRC and Clock Control Register Bit Descriptions Bit Name SRCDIV[1:0] CLK2DIV[1:0] CLK1DIV[1:0] MCLKSEL[1:0] Description Divides the SRC master clock. 00 = SRC master clock is not divided. 01 = SRC master clock is divided by 1.5.
PAGE 33
ADAV803 Playback Port Control—Address 0000100 (0x04) Table 21. Playback Port Control Register Bit Map 7 Reserved 6 Reserved 5 Reserved 4 CLKSRC1 3 CLKSRC0 2 SPMODE2 1 SPMODE1 0 SPMODE0 2 SPMODE2 1 SPMODE1 0 SPMODE0 Table 22. Playback Port Control Register Bit Descriptions Bit Name CLKSRC[1:0] SPMODE[2:0] Description Selects the clock source for generating the ILRCLK and IBCLK. 00 = Input port is a slave. 01 = Recovered PLL clock. 10 = Internal Clock 1. 11 = Internal Clock 2.
PAGE 34
ADAV803 Record Port Control—Address 0000110 (0x06) Table 25. Record Port Control Register Bit Map 7 Reserved 6 Reserved 5 CLKSRC1 4 CLKSRC0 3 WLEN1 2 WLEN0 1 SPMODE1 0 SPMODE0 2 WLEN0 1 SPMODE1 0 SPMODE0 Table 26. Record Port Control Register Bit Descriptions Bit Name CLKSRC[1:0] WLEN[1:0] SPMODE[1:0] Description Selects the clock source for generating the OLRCLK and OBCLK. 00 = Record port is a slave. 01 = Recovered PLL clock. 10 = Internal Clock 1. 11 = Internal Clock 2.
PAGE 35
ADAV803 Group Delay and Mute—Address 0001000 (0x08) Table 29. Group Delay and Mute Register Bit Map 7 MUTE_SRC 6 GRPDLY6 5 GRPDLY5 4 GRPDLY4 3 GRPDLY3 2 GRPDLY2 1 GRPDLY1 0 GRPDLY0 1 LOCK1 0 LOCK0 Table 30. Group Delay and Mute Register Bit Descriptions Bit Name MUTE_SRC Description Soft-mutes the output of the sample rate converter. 0 = No mute. 1 = Soft mute. Adds delay to the sample rate converter FIR filter by GRPDLY[6:0] input samples. 0000000 = No delay. 0000001 = 1 sample delay.
PAGE 36
ADAV803 Receiver Configuration 2—Address 0001010 (0x0A) Table 33. Receiver Configuration 2 Register Bit Map 7 RxMUTE 6 SP_PLL 5 SP_PLL_ SEL1 4 SP_PLL_ SEL0 3 Reserved 2 Reserved 1 NO NONAUDIO 0 NO_VALIDITY Table 34. Receiver Configuration 2 Register Bit Descriptions Bit Name RxMUTE SP_PLL SP_PLL_SEL[1:0] NO NONAUDIO NO_VALIDITY Description Hard-mutes the audio output for the AES3/S/PDIF receiver. 0 = AES3/S/PDIF receiver is not muted. 1 = AES3/S/PDIF receiver is muted.
PAGE 37
ADAV803 Receiver Buffer Configuration—Address 0001011 (0x0B) Table 35. Receiver Buffer Configuration Register Bit Map 7 Reserved 6 Reserved 5 RxBCONF5 4 RxBCONF4 3 RxBCONF3 2 RxBCONF2 1 RxBCONF1 0 RxBCONF0 Table 36.
PAGE 38
ADAV803 Transmitter Buffer Configuration—Address 0001101 (0x0D) Table 39. Transmitter Buffer Configuration Register Bit Map 7 IU_Zeros3 6 IU_Zeros2 5 IU_Zeros1 4 IU_Zeros0 3 TxBCONF3 2 TxBCONF2 1 TxBCONF1 0 TxBCONF0 Table 40. Transmitter Buffer Configuration Register Bit Descriptions Bit Name IU_Zeros[3:0] TxBCONF3 TxBCONF[2:1] TxBCONF0 Description Determines the number of zeros to be stuffed between IUs in a message up to a maximum of 8. 0000 = 0. 0001 = 1. … 0111 = 7. 1000 = 8.
PAGE 39
ADAV803 Transmitter Message Zeros Most Significant Byte—Address 0001111 (0x0F) Table 43. Transmitter Message Zeros Most Significant Byte Register Bit Map 7 MSBZeros7 6 MSBZeros6 5 MSBZeros5 4 MSBZeros4 3 MSBZeros3 2 MSBZeros2 1 MSBZeros1 0 MSBZeros0 Table 44. Transmitter Message Zeros Most Significant Byte Register Bit Description Bit Name MSBZeros[7:0] Description Most significant byte of the number of zeros to be stuffed between IEC60958-3 messages (packets). Default = 0x00.
PAGE 40
ADAV803 Sample Rate Ratio LSB—Address 0010011 (0x13) Table 51. Sample Rate Ratio LSB Register (Read-Only) Bit Map 7 SRCRATIO07 6 SRCRATIO06 5 SRCRATIO05 4 SRCRATIO04 3 SRCRATIO03 2 SRCRATIO02 1 SRCRATIO01 0 SRCRATIO00 2 PRE_C10 1 PRE_C9 0 PRE_C8 Table 52. Sample Rate Ratio LSB Register (Read-Only) Bit Descriptions Bit Name SRCRATIO[7:0] Description Eight least significant bits of the15-bit sample rate ratio. Preamble-C MSB—Address 0010100 (0x14) Table 53.
PAGE 41
ADAV803 Receiver Error—Address 0011000 (0x18) Table 61. Receiver Error Register (Read-Only) Bit Map 7 RxValidity 6 Emphasis 5 NonAudio 4 NonAudio Preamble 3 CRCError 2 NoStream 1 BiPhase/Parity 0 Lock Table 62. Receiver Error Register (Read-Only) Bit Descriptions Bit Name RxValidity Emphasis NonAudio NonAudio Preamble CRCError NoStream BiPhase/Parity Lock Description This is the VALIDITY bit in the AES3 received stream. This bit is set if the audio data is pre-emphasized.
PAGE 42
ADAV803 Sample Rate Converter Error—Address 0011010 (0x1A) Table 65. Sample Rate Converter Error Register (Read-Only) Bit Map 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 TOO_SLOW 2 OVRL 1 OVRR 0 MUTE_IND Table 66. Sample Rate Converter Error Register (Read-Only) Bit Descriptions Bit Name TOO_SLOW OVRL OVRR MUTE_IND Description This bit is set when the clock to the SRC is too slow, that is, there are not enough clock cycles to complete the internal convolution.
PAGE 43
ADAV803 Interrupt Status—Address 0011100 (0x1C) Table 69. Interrupt Status Register Bit Map 7 SRCError 6 TxCSTINT 5 TxUBINT 4 TxCSBINT 3 RxCSDIFF 2 RxUBINT 1 RxCSBINT 0 RxERROR Table 70. Interrupt Status Register Bit Descriptions Bit Name SRCError TxCSTINT TxUBINT TxCSBINT RxCSDIFF RxUBINT RxCSBINT RxERROR Description This bit is set if one of the sample rate converter interrupts is asserted, and the host should immediately read the sample rate converter error register.
PAGE 44
ADAV803 Mute and De-Emphasis—Address 0011110 (0x1E) Table 73. Mute and De-Emphasis Register Bit Map 7 Reserved 6 Reserved 5 TxMUTE 4 Reserved 3 Reserved 2 SRC_DEEM1 1 SRC_DEEM0 0 Reserved 1 NonAudio Subframe_A 0 NonAudio Subframe_B Table 74. Mute and De-Emphasis Register Bit Descriptions Bit Name TxMUTE Description Mutes the AES3/S/PDIF transmitter. 0 = Transmitter is not muted. 1 = Transmitter is muted. Selects the de-emphasis filter for the input data to the sample rate converter.
PAGE 45
ADAV803 Receiver User Bit Buffer Indirect Address— Address 1010000 (0x50) Table 81. Receiver User Bit Buffer Indirect Address Register Bit Map 7 RxUBADDR7 6 RxUBADDR6 5 RxUBADDR5 4 RxUBADDR4 3 RxUBADDR3 2 RxUBADDR2 1 RxUBADDR1 0 RxUBADDR0 1 RxUBDATA1 0 RxUBDATA0 Table 82. Receiver User Bit Buffer Indirect Address Register Bit Descriptions Bit Name RxUBADDR[7:0] Description Indirect address pointing to the address location in the receiver user bit buffer.
PAGE 46
ADAV803 Q Subcode Buffer—Address 0x55 to Address 0x5E Table 91.
PAGE 47
ADAV803 Datapath Control Register 2—Address 1100011 (0x63) Table 94. Datapath Control Register 2 Bit Map 7 Reserved 6 Reserved 5 DAC2 4 DAC1 3 DAC0 2 DIT2 1 DIT1 0 DIT0 3 POL1 2 POL0 1 MUTER 0 MUTEL Table 95. Datapath Control Register 2 Bit Descriptions Bit Name DAC[2:0] DIT[2:0] Description Datapath source select for DAC. 00 = ADC. 01 = DIR. 10 = Playback. 11 = Auxiliary in. 100 = SRC. Datapath source select for DIT. 000 = ADC. 001 = DIR. 010 = Playback. 011 = Auxiliary in. 100 = SRC.
PAGE 48
ADAV803 DAC Control Register 2—Address 1100101 (0x65) Table 98. DAC Control Register 2 Bit Map 7 Reserved 6 Reserved 5 DMCLK1 4 DMCLK0 3 DFS1 2 DFS0 1 DEEM1 0 DEEM0 3 Reserved 2 ZFVOL 1 ZFDATA 0 ZFPOL Table 99. DAC Control Register 2 Bit Descriptions Bit Name DMCLK[1:0] DFS[1:0] DEEM[1:0] Description DAC MCLK divider. 00 = MCLK. 01 = MCLK/1.5. 10 = MCLK/2. 11 = MCLK/3. DAC interpolator select. 00 = 8 × (MCLK = 256 × fS). 01 = 4 × (MCLK = 128 × fS). 10 = 2 × (MCLK = 64 × fS). 11 = Reserved.
PAGE 49
ADAV803 DAC Control Register 4—Address 1100111 (0x67) Table 102. DAC Control Register 4 Bit Map 7 Reserved 6 INTRPT 5 ZEROSEL1 4 ZEROSEL0 3 Reserved 2 Reserved 1 Reserved 0 Reserved Table 103. DAC Control Register 4 Bit Descriptions Bit Name INTRPT ZEROSEL[1:0] Description This bit selects the functionality of the ZEROL/INT pin. 0 = Pin functions as a ZEROL flag pin. 1 = Pin functions as an interrupt pin.
PAGE 50
ADAV803 DAC Right Peak Volume—Address 1101011 (0x6B) Table 110. DAC Right Peak Volume Register Bit Map 7 Reserved 6 Reserved 5 DRP5 4 DRP4 3 DRP3 2 DRP2 1 DRP1 0 DRP0 3 AGL3 2 AGL2 1 AGL1 0 AGL0 3 AGR3 2 AGR2 1 AGR1 0 AGR0 Table 111. DAC Right Peak Volume Register Bit Descriptions Bit Name DRP[5:0] Description DAC right channel peak volume detection. 000000 = 0 dBFS. 000001 = −1 dBFS. 111111 = −63 dBFS. ADC Left Channel PGA Gain—Address 1101100 (0x6C) Table 112.
PAGE 51
ADAV803 ADC Control Register 1—Address 1101110 (0x6E) Table 116. ADC Control Register 1 Bit Map 7 AMC 6 HPF 5 PWRDWN 4 ANA_PD 3 MUTER 2 MUTEL 1 PLPD 0 PRPD 3 Reserved 2 Reserved 1 MCD1 0 MCD0 Table 117. ADC Control Register 1 Bit Descriptions Bit Name AMC HPF PWRDWN ANA_PD MUTER MUTEL PLPD PRPD Description ADC modulator clock. 0 = ADC MCLK/2 (128 × fS). 1 = ADC MCLK/4 (64 × fS). High-pass filter enable. 0 = Normal. 1 = HPF enabled. ADC power-down. 0 = Normal. 1 = Power-down.
PAGE 52
ADAV803 ADC Left Volume—Address 1110000 (0x70) Table 120. ADC Left Volume Register Bit Map 7 AVOLL7 6 AVOLL6 5 AVOLL5 4 AVOLL4 3 AVOLL3 2 AVOLL2 1 AVOLL1 0 AVOLL0 3 AVOLR3 2 AVOLR2 1 AVOLR1 0 AVOLR0 3 ALP3 2 ALP2 1 ALP1 0 ALP0 3 ARP3 2 ARP2 1 ARP1 0 ARP0 Table 121. ADC Left Volume Register Bit Descriptions Bit Name AVOLL[7:0] Description ADC left channel volume control. 1111111 = 1.0 (0 dBFS). 1111110 = 0.996 (−0.00348 dBFS). 1000000 = 0.5 (−6 dBFS). 0111111 = 0.496 (−6.09 dBFS).
PAGE 53
ADAV803 PLL Control Register 1—Address 1110100 (0x74) Table 128. PLL Control Register 1 Bit Map 7 DIRIN_CLK1 6 DIRIN_CLK0 5 MCLKODIV 4 PLLDIV 3 PLL2PD Table 129. PLL Control Register 1 Bit Descriptions Bit Name DIRIN_CLK[1:0] MCLKODIV PLLDIV PLL2PD PLL1PD XTLPD SYSCLK3 Description Recovered S/PDIF clock sent to SYSCLK3. 00 = SYSCLK3 comes from PLL block. 01 = Reserved. 10 = Reserved. 11 = SYSCLK3 is the recovered S/PDIF clock from DIRIN. Divide input MCLK by 2 to generate MCLKO. 0 = Disabled.
PAGE 54
ADAV803 PLL Control Register 2—Address 1110101 (0x75) Table 130. PLL Control Register 2 Bit Map 7 FS2_1 6 FS2_0 5 SEL2 4 DOUB2 3 FS1 Table 131. PLL Control Register 2 Bit Descriptions Bit Name FS2_[1:0] SEL2 DOUB2 FS[1:0] SEL1 DOUB1 Description Sample rate select for PLL2. 00 = 48 kHz. 01 = Reserved. 10 = 32 kHz. 11 = 44.1 kHz. Oversample ratio select for PLL2. 0 = 256 × fS. 1 = 384 × fS. Double-selected sample rate on PLL2. 0 = Disabled. 1 = Enabled. Sample rate select for PLL1. 00 = 48 kHz.
PAGE 55
ADAV803 Internal Clocking Control Register 1—Address 1110110 (0x76) Table 132. Internal Clocking Control Register 1 Bit Map 7 DCLK2 6 DCLK1 5 DCLK0 4 ACLK2 3 ACLK1 2 ACLK0 1 ICLK2_1 0 ICLK2_0 3 ICLK1_0 2 PLL2INT1 1 PLL2INT0 0 PLL1INT Table 133. Internal Clocking Control Register 1 Bit Descriptions Bit Name DCLK[2:0] ACLK[2:0] ICLK2_[1:0] Description DAC clock source select. 000 = XIN. 001 = MCLKI. 010 = PLLINT1. 011 = PLLINT2. 100 = DIR PLL (512 × fS). 101 = DIR PLL (256 × fS). 110 = XIN.
PAGE 56
ADAV803 PLL Clock Source Register—Address 1111000 (0x78) Table 136. PLL Clock Source Register Bit Map 7 PLL2_Source 6 PLL1_Source 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 Reserved 3 Reserved 2 SYSCLK1 1 SYSCLK2 0 SYSCLK3 Table 137. PLL Clock Source Register Bit Descriptions Bit Name PLL2_Source PLL1_Source Description Selects the clock source for PLL2. 0 = XIN. 1 = MCLKI. Selects the clock source for PLL1. 0 = XIN. 1 = MCLKI PLL Output Enable—Address 1111010 (0x7A) Table 138.
PAGE 57
ADAV803 ALC Control Register 1—Address 1111011 (0x7B) Table 140. ALC Control Register 1 Bit Map 7 FSSEL1 6 FSSEL0 5 GAINCNTR1 4 GAINCNTR0 3 RECMODE1 2 RECMODE0 Table 141. ALC Control Register 1 Bit Descriptions Bit Name FSSEL[1:0] GAINCNTR[1:0] RECMODE[1:0] LIMDET ALCEN Description These bits should equal the sample rate of the ADC. 00 = 96 kHz. 01 = 48 kHz. 10 = 32 kHz. 11 = Reserved. These bits determine the limit of the counter used in limited recovery mode. 00 = 3. 01 = 7. 10 = 15. 11 = 31.
PAGE 58
ADAV803 ALC Control Register 2— Address = 1111100 (0x7C) Table 142. ALC Control Register 2 Bit Map 7 Reserved 6 RECTH1 5 RECTH0 4 ATKTH1 3 ATKTH0 2 RECTIME1 1 RECTIME0 0 ATKTIME 3 ALC RESET 2 ALC RESET 1 ALC RESET 0 ALC RESET Table 143. ALC Control Register 2 Bit Descriptions Bit Name RECTH[1:0] ATKTH[1:0] RECTIME[1:0] ATKTIME Description Recovery threshold. 00 = −2 dB. 01 = −3 dB. 10 = −4 dB. 11 = −6 dB. Attack threshold. 00 = 0 dB. 01 = −1 dB. 10 = −2 dB. 11 = −4 dB.
PAGE 59
ADAV803 LAYOUT CONSIDERATIONS Getting the best performance from the ADAV803 requires a careful layout of the printed circuit board (PCB). Using separate analog and digital ground planes is recommended, because these give the currents a low resistance path back to the power supplies. The ground planes should be connected in only one place, usually under the ADAV803, to prevent ground loops.
PAGE 60
ADAV803 OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 64 49 1 48 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY 16 33 32 17 VIEW A VIEW A 0.50 BSC LEAD PITCH ROTATED 90° CCW 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-BCD 051706-A 1.45 1.40 1.35 Figure 55.