Datasheet

ADAV801
Rev. A | Page 56 of 60
ALC Control Register 1—Address 1111011 (0x7B)
Table 140. ALC Control Register 1 Bit Map
7 6 5 4 3 2 1 0
FSSEL1 FSSEL0 GAINCNTR1 GAINCNTR0 RECMODE1 RECMODE0 LIMDET ALCEN
Table 141. ALC Control Register 1 Bit Descriptions
Bit Name Description
FSSEL[1:0] These bits should equal the sample rate of the ADC.
00 = 96 kHz.
01 = 48 kHz.
10 = 32 kHz.
11 = Reserved.
GAINCNTR[1:0] These bits determine the limit of the counter used in limited recovery mode.
00 = 3.
01 = 7.
10 = 15.
11 = 31.
RECMODE[1:0] These bits determine which recovery mode is used by the ALC section.
00 = No recovery.
01 = Normal recovery.
10 = Limited recovery.
11 = Reserved.
LIMDET These bits limit detect mode.
0 = ALC is used when either channel exceeds the set limit.
1 = ALC is used only when both channels exceed the set limit.
ALCEN These bits enable ALC.
0 = Disable ALC.
1 = Enable ALC.