Datasheet

ADAV801
Rev. A | Page 47 of 60
DAC Control Register 2—Address 1100101 (0x65)
Table 98. DAC Control Register 2 Bit Map
7 6 5 4 3 2 1 0
Reserved Reserved DMCLK1 DMCLK0 DFS1 DFS0 DEEM1 DEEM0
Table 99. DAC Control Register 2 Bit Descriptions
Bit Name Description
DMCLK[1:0] DAC MCLK divider.
00 = MCLK.
01 = MCLK/1.5.
10 = MCLK/2.
11 = MCLK/3.
DFS[1:0] DAC interpolator select.
00 = 8 × (MCLK = 256 × f
S
).
01 = 4 × (MCLK = 128 × f
S
).
10 = 2 × (MCLK = 64 × f
S
).
11 = Reserved.
DEEM[1:0] DAC de-emphasis select.
00 = None.
01 = 44.1 kHz.
10 = 32 kHz.
11 = 48 kHz.
DAC Control Register 3—Address 1100110 (0x66)
Table 100. DAC Control Register 3 Bit Map
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved Reserved ZFVOL ZFDATA ZFPOL
Table 101. DAC Control Register 3 Bit Descriptions
Bit Name Description
ZFVOL DAC zero flag on mute and zero volume.
0 = Enabled.
1 = Disabled.
ZFDATA DAC zero flag on zero data disable.
0 = Enabled.
1 = Disabled.
ZFPOL DAC zero flag polarity.
0 = Active low.
1 = Active high.