Datasheet

ADAV801
Rev. A | Page 46 of 60
Datapath Control Register 2—Address 1100011 (0x63)
Table 94. Datapath Control Register 2 Bit Map
7 6 5 4 3 2 1 0
Reserved Reserved DAC2 DAC1 DAC0 DIT2 DIT1 DIT0
Table 95. Datapath Control Register 2 Bit Descriptions
Bit Name Description
DAC[2:0] Datapath source select for DAC.
00 = ADC.
01 = DIR.
10 = Playback.
11 = Auxiliary in.
100 = SRC.
DIT[2:0] Datapath source select for DIT.
000 = ADC.
001 = DIR.
010 = Playback.
011 = Auxiliary in.
100 = SRC.
DAC Control Register 1—Address 1100100 (0x64)
Table 96. DAC Control Register 1 Bit Map
7 6 5 4 3 2 1 0
DR_ALL DR_DIG CHSEL1 CHSEL0 POL1 POL0 MUTER MUTEL
Table 97. DAC Control Register 1 Bit Descriptions
Bit Name Description
DR_ALL Hard reset and power-down.
0 = Normal, output pins go to V
REF
level.
1 = Hard reset and low power, output pins go to AGND.
DR_DIG DAC digital reset.
0 = Normal.
1 = Reset all except registers.
CHSEL[1:0] DAC channel select.
00 = Normal, left-right.
01 = Both right.
10 = Both left.
11 = Swapped, right-left.
POL[1:0] DAC channel polarity.
00 = Both positive.
01 = Left negative.
10 = Right negative.
11 = Both negative.
MUTER Mute right channel.
0 = Mute.
1 = Normal.
MUTEL Mute left channel.
0 = Mute.
1 = Normal.