Datasheet
ADAV801
Rev. A | Page 41 of 60
Sample Rate Converter Error—Address 0011010 (0x1A)
Table 65. Sample Rate Converter Error Register (Read-Only) Bit Map
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved TOO_SLOW OVRL OVRR MUTE_IND
Table 66. Sample Rate Converter Error Register (Read-Only) Bit Descriptions
Bit Name Description
TOO_SLOW
This bit is set when the clock to the SRC is too slow, that is, there are not enough clock cycles to complete the
internal convolution.
OVRL
This bit is set when the left output data of the sample rate converter has gone over the full-scale range and has been
clipped. This bit is not cleared until the register is read.
OVRR
This bit is set when the right output data of the sample rate converter has gone over the full-scale range and has
been clipped. This bit is not cleared until the register is read.
MUTE_IND
Mute indicated. This bit is set when the SRC is in fast mode and clicks or pops can be heard in the SRC output data.
The output of the SRC can be muted, if required, until the SRC is in slow mode. Once read, this bit remains in its state
and does not generate an interrupt until it has changed state.
Sample Rate Converter Error Mask—Address 0011011 (0x1B)
Table 67. Sample Rate Converter Error Mask Register Bit Map
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved Reserved OVRL Mask OVRR Mask MUTE_IND MASK
Table 68. Sample Rate Converter Error Mask Register Bit Descriptions
Bit Name Description
OVRL Mask Masks the OVRL from generating an interrupt.
0 = OVRL bit does not generate an interrupt.
1 = OVRL bit generates an interrupt.
OVRR Mask Masks the OVRR from generating an interrupt.
0 = OVRR bit does not generate an interrupt.
1 = OVRR bit generates an interrupt. Reserved.
MUTE_IND MASK Masks the MUTE_IND from generating an interrupt.
0 = MUTE_IND bit does not generate an interrupt.
1 = MUTE_IND bit generates an interrupt.