Datasheet

ADAV801
Rev. A | Page 32 of 60
Playback Port Control—Address 0000100 (0x04)
Table 21. Playback Port Control Register Bit Map
7 6 5 4 3 2 1 0
Reserved Reserved Reserved CLKSRC1 CLKSRC0 SPMODE2 SPMODE1 SPMODE0
Table 22. Playback Port Control Register Bit Descriptions
Bit Name Description
CLKSRC[1:0] Selects the clock source for generating the ILRCLK and IBCLK.
00 = Input port is a slave.
01 = Recovered PLL clock.
10 = Internal Clock 1.
11 = Internal Clock 2.
SPMODE[2:0] Selects the serial format of the playback port.
000 = Left-justified.
001 = I
2
S.
100 = 24-bit, right-justified.
101 = 20-bit, right-justified.
110 = 18-bit, right-justified.
111 = 16-bit, right-justified.
Auxiliary Input Port—Address 0000101 (0x05)
Table 23. Auxiliary Input Port Register Bit Map
7 6 5 4 3 2 1 0
Reserved Reserved Reserved CLKSRC1 CLKSRC0 SPMODE2 SPMODE1 SPMODE0
Table 24. Auxiliary Input Port Register Bit Descriptions
Bit Name Description
CLKSRC[1:0] Selects the clock source for generating the IAUXLRCLK and IAUXBCLK.
00 = Input port is a slave.
01 = Recovered PLL cock.
10 = Internal Clock 1.
11 = Internal Clock 2.
SPMODE[2:0] Selects the serial format of auxiliary input port.
000 = Left-justified.
001 = I
2
S.
100 = 24-bit, right-justified.
101 = 20-bit, right-justified.
110 = 18-bit, right-justified.
111 = 16-bit, right-justified.