Datasheet

Data Sheet ADAU1966
Rev. D | Page 7 of 52
Parameter Mode Factor Min Typ Max Unit
Propagation Delay 48 kHz mode, typical at 48 kHz 25/f
S
521 µs
96 kHz mode, typical at 96 kHz 11/f
S
115 µs
192 kHz mode, typical at 192 kHz 8/f
S
42 µs
192 kHz low delay mode, typical at 192 kHz 2/f
S
10 µs
TIMING SPECIFICATIONS
−40°C < T
A
< +105°C, DVDD = 2.5 V ± 10%.
Table 7.
Parameter
Description
Min
Typ
Max
Unit
INPUT MASTER CLOCK (MCLK) AND RESET
t
MH
MCLK duty cycle, DAC clock source = PLL clock at
256 × f
S
, 384 × f
S
, 512 × f
S
, and 768 × f
S
40 60 %
t
MH
DAC clock source = direct MCLK at 512 × f
S
(bypass
on-chip PLL)
40 60 %
f
MCLK
MCLKI frequency, PLL mode 6.9 40.5 MHz
f
MCLK
Direct MCLK 512 × f
S
mode 27.1 MHz
f
BCLK
DBCLK frequency, PLL mode
27.0
MHz
t
PDR
Low 15 ns
t
PDRR
Recovery, reset to active output 300 ms
PLL
Lock Time MCLK input 10 ms
Lock Time DLRCLK input 50 ms
256 × f
S
VCO Clock, Output Duty Cycle, MCLKO Pin 40 60 %
SPI PORT See Figure 17
t
CCH
CCLK high 35 ns
t
CCL
CCLK low 35 ns
f
CCLK
CCLK frequency, f
CCLK
= 1/t
CCP
; only t
CCP
shown in Figure 17 10 MHz
t
CDS
CDATA setup, time to CCLK rising
10
ns
t
CDH
CDATA hold, time from CCLK rising 10 ns
t
CLS
CLATCH setup, time to CCLK rising
10 ns
t
CLH
CLATCH hold, time from CCLK falling
10 ns
t
CLHIGH
CLATCH high, not shown in Figure 17
10 ns
t
COE
COUT enable from CCLK falling 30 ns
t
COD
COUT delay from CCLK falling 30 ns
t
COH
COUT hold from CCLK falling, not shown in Figure 17 30 ns
t
COTS
COUT tristate from CCLK falling 30 ns
I
2
C See Figure 2 and Figure 13
f
SCL
SCL clock frequency 400 kHz
t
SCLL
SCL low
1.3
µs
t
SCLH
SCL high 0.6 µs
t
SCS
Setup time (start condition), relevant for repeated start
condition
0.6 µs
t
SCH
Hold time (start condition), first clock generated after
this period
0.6 µs
t
SSH
Setup time (stop condition)
0.6
µs
t
DS
Data setup time 100 ns
t
SR
SDA and SCL rise time 300 ns
t
SF
SDA and SCL fall time 300 ns
t
BFT
Bus-free time between stop and start 1.3 µs