Datasheet

ADAU1772 Data Sheet

Rev. B | Page 90 of 116

SERIAL PORT CONTROL 1 REGISTER

Address: 0x0033, Reset: 0x00, Name: SAI_1

Using 16-bit serial I/O limits device performance.

Table 80. Bit Descriptions for SAI_1

Bits Bit Name Settings Description Reset Access

7 TDM_TS Select whether to tristate unused TDM channels or to actively drive these

data slots.

0x0 RW

0 Unused outputs driven

1 Unused outputs tristated

BCLK_TDMC

Bit width in TDM mode.

0x0

0 24-bit data in each TDM channel

1 16-bit data in each TDM channel

5 LR_MODE Sets LRCLK mode. 0x0 RW

0 50% duty cycle clock

1 Pulse—LRCLK is a single BCLK cycle wide pulse

LR_POL

Sets LRCLK polarity.

0x0

0 50%: when LRCLK goes low and then high, pulse mode is short positive pulse

1 50%: when LRCLK goes high and then low, pulse mode is short negative pulse

3 SAI_MSB Sets data to be input/output either MSB or LSB first. 0x0 RW

0 MSB first data

1 LSB first data

2 BCLKRATE Sets the number of bit clock cycles per data channel. 0x0 RW

0 32 BCLK cycles/channel

1 16 BCLK cycles/channel

1 BCLKEDGE Sets the bit clock edge on which data changes. 0x0 RW

0 Data changes on falling edge

1 Data changes on rising edge

0 SAI_MS Sets the serial port into master or slave mode. 0x0 RW

0 LRCLK/BCLK slave

1 LRCLK/BCLK master