Datasheet

Data Sheet ADAU1772

Rev. B | Page 75 of 116

ADC0/ADC1 CONTROL 1 REGISTER

Address: 0x001D, Reset: 0x00, Name: ADC_CONTROL2

Table 58. Bit Descriptions for ADC_CONTROL2

Bits Bit Name Settings Description Reset Access

[6:5] HP_0_1_EN High-pass filter settings. 0x0 RW

00 Off

01 1 Hz

10 4 Hz

11 8 Hz

DMIC_POL0

Selects microphone polarity.

0x0

0 0 positive, 1 negative

1 1 positive, 0 negative

3 DMIC_SW0 Digital microphone swap. 0x0 RW

0 Channel swap off (left channel on rising edge, right channel on falling edge)

1 Swap left and right

2 DCM_0_1 Sets the input source to ADCs or digital microphones. 0x0 RW

0 Decimator source set to ADC

1 Decimator source set to digital microphones

1 ADC_1_EN Enable ADC1. This bit must be set in conjunction with the SINC_1_EN bit

in the DECIM_PWR_MODES register to fully enable or disable the ADC.

0x0 RW

0 Disable

1 Enable

0 ADC_0_EN Enable ADC0. This bit must be set in conjunction with the SINC_0_EN bit

in the DECIM_PWR_MODES register to fully enable or disable the ADC.

0x0 RW

0 Disable

1 Enable