Datasheet

Data Sheet ADAU1772
Rev. B | Page 63 of 116
DAC INPUT SELECT REGISTER
Address: 0x0011, Reset: 0x10, Name: DAC_SOURCE_0_1
Table 46. Bit Descriptions for DAC_SOURCE_0_1
Bits Bit Name Settings Description Reset Access
[7:4] DAC_SOURCE1 DAC1 input source. This setting should not be changed while the core is
running. CORE_RUN must be set to 0 for this setting to be updated.
0x1 RW
0000 Core Output 0
0001 Core Output 1
0010 Core Output 2
0011 Core Output 3
0100 Reserved
0101 Reserved
0110 Reserved
0111
Reserved
1000 Reserved
1001 Reserved
1010 Reserved
1011 Reserved
1100 Input ASRC Channel 0
1101 Input ASRC Channel 1
[3:0] DAC_SOURCE0 DAC0 input source. This setting should not be changed while the core is
running. CORE_RUN must be set to 0 for this setting to be updated.
0x0 RW
0000 Core Output 0
0001 Core Output 1
0010 Core Output 2
0011 Core Output 3
0100 Reserved
0101
Reserved
0110 Reserved
0111 Reserved
1000 Reserved
1001 Reserved
1010 Reserved
1011 Reserved
1100 Input ASRC Channel 0
1101 Input ASRC Channel 1