Datasheet

ADAU1772 Data Sheet

Rev. B | Page 62 of 116

CORE CHANNEL 2/CORE CHANNEL 3 INPUT SELECT REGISTER

Address: 0x0010, Reset: 0x32, Name: CORE_IN_MUX_2_3

Table 45. Bit Descriptions for CORE_IN_MUX_2_3

Bits

Bit Name

Settings

Description

Reset

Access

[7:4] CORE_IN_MUX_SEL_3 Core Input Channel 3 source. 0x3 RW

0000 AIN0/DMIC0

0001 AIN1/DMIC1

0010 AIN2/DMIC2

0011 AIN3/DMIC3

0100 Reserved

0101 Reserved

0110 Reserved

0111 Reserved

1000 Reserved

1001 Reserved

1010 Reserved

1011

Reserved

1100 Input ASRC Channel 0

1101 Input ASRC Channel 1

[3:0] CORE_IN_MUX_SEL_2 Core Input Channel 2 source. 0x2 RW