Datasheet

Data Sheet ADAU1772
Rev. B | Page 57 of 116
CORE CONTROL REGISTER
Address: 0x0009, Reset: 0x04, Name: CORE_CONTROL
Table 39. Bit Descriptions for CORE_CONTROL
Bits Bit Name Settings Description Reset Access
7 ZERO_STATE Zeroes the state of the data memory during bank switching. When
switching active parameter banks between two settings, zeroing the state
of the bank prevents the new filter settings from being active on old data
that is recirculating in filters. Zeroing the state may prevent filter
instability or unwanted noises upon bank switching.
0x0 RW
0 Do not zero state during bank switch
1 Zero state during back switch
[6:5] BANK_SL Selects active filter bank. 0x0 RW
00 Bank A active
01 Bank B active
10 Reserved
11 Reserved
[2:1] CORE_FS This bit sets the core sample rate. This setting should not be changed
while the core is running. CORE_RUN must be set to 0 for this setting to be
updated.
00 Reserved
01 96 kHz
10 192 kHz
11 Reserved
0 CORE_RUN Run bit for the core. This bit should only be enabled when the program
and parameters are loaded and the sample rate settings have been set.
CORE_RUN starts and stops the core at the beginning of the program.
0x0 RW
0
Core off
1 Core on