Datasheet

ADAU1772 Data Sheet
Rev. B | Page 56 of 116
Table 37. Bit Descriptions for CLKOUT_SEL
Bits Bit Name Settings Description Reset Access
[2:0] CLKOUT_FREQ CLKOUT pin frequency. 0x0 RW
000 Master clock × 2 (24.576 MHz)
001 Master clock (12.288 MHz)
010 Master clock/2 (6.144 MHz)
011 Master clock/4 (3.072 MHz)
100 Master clock/8 (1.536 MHz)
111 Clock output off = 0
REGULATOR CONTROL REGISTER
Address: 0x0008, Reset: 0x00, Name: REGULATOR
Table 38. Bit Descriptions for REGULATOR
Bits Bit Name Settings Description Reset Access
2 REG_PD Powers down LDO regulator. 0x0 RW
0 Regulator active
1 Regulator powered down
[1:0] REGV Set regulator output voltage. 0x0 RW
00 1.2 V
01 1.1 V
10 Reserved
11 Reserved