Datasheet

Data Sheet ADAU1772
Rev. B | Page 55 of 116
Bits Bit Name Settings Description Reset Access
[2:1] X PLL input clock divide ratio. 0x0 RW
00 Pin clock input/1
01 Pin clock input/2
10 Pin clock input/3
11 Pin clock input/4
0 PLL_TYPE PLL type. 0x0 RW
0 Integer
1 Fractional
PLL LOCK FLAG REGISTER
Address: 0x0006, Reset: 0x00, Name: PLL_CTRL5
Table 36. Bit Descriptions for PLL_CTRL5
Bits Bit Name Settings Description Reset Access
0 LOCK Flag to indicate if the PLL is locked. This bit is read only. 0x0 R
0 PLL unlocked
1 PLL locked
CLKOUT SETTING SELECTION REGISTER
Address: 0x0007, Reset: 0x00, Name: CLKOUT_SEL
When Pin ADC_SDATA1/CLKOUT/MP6 is set to clock output mode, the frequency of the output clock is set here. CLKOUT can be used
to provide a master clock to another IC, the clock for digital microphones, or as the clock for the PDM output stream. The 12 MHz/24
MHz setting is used when clocking another IC, 3 MHz/6 MHz for PDMOUT, and 1.5 MHz/3 MHz when clocking digital microphones.
The CLKOUT frequency is derived from the master clock frequency, which is assumed to (and always should) be 12.288 MHz. The
12.288 MHz and 24.576 MHz output modes are not functional if PDM is enabled (Register PDM_OUT, Bits[1:0]).