Datasheet
ADAU1772 Data Sheet
Rev. B | Page 50 of 116
REGISTER SUMMARY
Table 29. Low Latency Codec Register Summary
Reg
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RW
0x0000
CLK_CONTROL
[7:0]
PLL_EN
RESERVED
SPK_FLT_DIS
XTAL_DIS
CLKSRC
CC_CDIV
CC_MDIV
COREN
0x00
RW
0x0001
PLL_CTRL0
[7:0]
M_MSB
0x00
RW
0x0002
PLL_CTRL1
[7:0]
M_LSB
0x00
RW
0x0003
PLL_CTRL2
[7:0]
N_MSB
0x00
RW
0x0004
PLL_CTRL3
[7:0]
N_LSB
0x00
RW
0x0005
PLL_CTRL4
[7:0]
RESERVED
R
X
PLL_TYPE
0x00
RW
0x0006
PLL_CTRL5
[7:0]
RESERVED
LOCK
0x00
R
0x0007
CLKOUT_SEL
[7:0]
RESERVED
CLKOUT_FREQ
0x00
RW
0x0008
REGULATOR
[7:0]
RESERVED
REG_PD
REGV
0x00
RW
0x0009
CORE_CONTROL
[7:0]
ZERO_STATE
BANK_SL
RESERVED
CORE_FS
CORE_RUN
0x04
RW
0x000B
CORE_ENABLE
[7:0]
RESERVED
LIM_EN
DSP_CLK_EN
0x03
RW
0x000C
DBREG0
[7:0]
DBVAL0
0x00
R
0x000D
DBREG1
[7:0]
DBVAL1
0x00
R
0x000E
DBREG2
[7:0]
DBVAL2
0x00
R
0x000F
CORE_IN_MUX_0_1
[7:0]
CORE_IN_MUX_SEL_1
CORE_IN_MUX_SEL_0
0x10
RW
0x0010
CORE_IN_MUX_2_3
[7:0]
CORE_IN_MUX_SEL_3
CORE_IN_MUX_SEL_2
0x32
RW
0x0011
DAC_SOURCE_0_1
[7:0]
DAC_SOURCE1
DAC_SOURCE0
0x10
RW
0x0012
PDM_SOURCE_0_1
[7:0]
PDM_SOURCE1
PDM_SOURCE0
0x32
RW
0x0013
SOUT_SOURCE_0_1
[7:0]
SOUT_SOURCE1
SOUT_SOURCE0
0x54
RW
0x0014
SOUT_SOURCE_2_3
[7:0]
SOUT_SOURCE3
SOUT_SOURCE2
0x76
RW
0x0015
SOUT_SOURCE_4_5
[7:0]
SOUT_SOURCE5
SOUT_SOURCE4
0x54
RW
0x0016
SOUT_SOURCE_6_7
[7:0]
SOUT_SOURCE7
SOUT_SOURCE6
0x76
RW
0x0017
ADC_SDATA_CH
[7:0]
RESERVED
ADC_SDATA1_ST
ADC_SDATA0_ST
0x04
RW
0x0018
ASRCO_SOURCE_0_1
[7:0]
ASRC_OUT_SOURCE1
ASRC_OUT_SOURCE0
0x10
RW
0x0019
ASRCO_SOURCE_2_3
[7:0]
ASRC_OUT_SOURCE3
ASRC_OUT_SOURCE2
0x32
RW
0x001A
ASRC_MODE
[7:0]
RESERVED
ASRC_IN_CH
ASRC_OUT_EN
ASRC_IN_EN
0x00
RW
0x001B
ADC_CONTROL0
[7:0]
RESERVED
RESERVED
ADC1_MUTE
ADC0_MUTE
RESERVED
ADC_0_1_FS
0x19
RW
0x001C
ADC_CONTROL1
[7:0]
RESERVED
RESERVED
ADC3_MUTE
ADC2_MUTE
RESERVED
ADC_2_3_FS
0x19
RW
0x001D
ADC_CONTROL2
[7:0]
RESERVED
HP_0_1_EN
DMIC_POL0
DMIC_SW0
DCM_0_1
ADC_1_EN
ADC_0_EN
0x00
RW
0x001E
ADC_CONTROL3
[7:0]
RESERVED
HP_2_3_EN
DMIC_POL1
DMIC_SW1
DCM_2_3
ADC_3_EN
ADC_2_EN
0x00
RW
0x001F
ADC0_VOLUME
[7:0]
ADC_0_VOL
0x00
RW
0x0020
ADC1_VOLUME
[7:0]
ADC_1_VOL
0x00
RW
0x0021
ADC2_VOLUME
[7:0]
ADC_2_VOL
0x00
RW
0x0022
ADC3_VOLUME
[7:0]
ADC_3_VOL
0x00
RW
0x0023
PGA_CONTROL_0
[7:0]
PGA_EN0
PGA_MUTE0
PGA_GAIN0
0x40
RW
0x0024
PGA_CONTROL_1
[7:0]
PGA_EN1
PGA_MUTE1
PGA_GAIN1
0x40
RW
0x0025
PGA_CONTROL_2
[7:0]
PGA_EN2
PGA_MUTE2
PGA_GAIN2
0x40
RW
0x0026
PGA_CONTROL_3
[7:0]
PGA_EN3
PGA_MUTE3
PGA_GAIN3
0x40
RW
0x0027
PGA_STEP_CONTROL
[7:0]
RESERVED
SLEW_RATE
SLEW_PD3
SLEW_PD2
SLEW_PD1
SLEW_PD0
0x00
RW
0x0028
PGA_10DB_BOOST
[7:0]
RESERVED
PGA_3_BOOST
PGA_2_BOOST
PGA_1_BOOST
PGA_0_BOOST
0x00
RW
0x0029
POP_SUPPRESS
[7:0]
RESERVED
HP_POP_DIS1
HP_POP_DIS0
PGA_POP_DIS3
PGA_POP_DIS2
PGA_POP_DIS1
PGA_POP_DIS0
0x3F
RW
0x002A
TALKTHRU
[7:0]
RESERVED
TALKTHRU_PATH
0x00
RW
0x002B
TALKTHRU_GAIN0
[7:0]
TALKTHRU_GAIN0_VAL
0x00
RW
0x002C
TALKTHRU_GAIN1
[7:0]
TALKTHRU_GAIN1_VAL
0x00
RW
0x002D
MIC_BIAS
[7:0]
RESERVED
MIC_EN1
MIC_EN0
RESERVED
RESERVED
MIC_GAIN1
MIC_GAIN0
0x00
RW
0x002E
DAC_CONTROL1
[7:0]
RESERVED
DAC_POL
DAC1_MUTE
DAC0_MUTE
RESERVED
DAC1_EN
DAC0_EN
0x18
RW
0x002F
DAC0_VOLUME
[7:0]
DAC_0_VOL
0x00
RW
0x0030
DAC1_VOLUME
[7:0]
DAC_1_VOL
0x00
RW
0x0031
OP_STAGE_MUTES
[7:0]
RESERVED
HP_MUTE_R
HP_MUTE_L
0x0F
RW
0x0032
SAI_0
[7:0]
SDATA_FMT
SAI
SER_PORT_FS
0x00
RW
0x0033
SAI_1
[7:0]
TDM_TS
BCLK_TDMC
LR_MODE
LR_POL
SAI_MSB
BCLKRATE
BCLKEDGE
SAI_MS
0x00
RW
0x0034
SOUT_CONTROL0
[7:0]
TDM7_DIS
TDM6_DIS
TDM5_DIS
TDM4_DIS
TDM3_DIS
TDM2_DIS
TDM1_DIS
TDM0_DIS
0x00
RW
0x0036
PDM_OUT
[7:0]
RESERVED
PDM_CTRL
PDM_CH
PDM_EN
0x00
RW
0x0037
PDM_PATTERN
[7:0]
PATTERN
0x00
RW
0x0038
MODE_MP0
[7:0]
RESERVED
MODE_MP0_VAL
0x00
RW
0x0039
MODE_MP1
[7:0]
RESERVED
MODE_MP1_VAL
0x10
RW
0x003A
MODE_MP2
[7:0]
RESERVED
MODE_MP2_VAL
0x00
RW
0x003B
MODE_MP3
[7:0]
RESERVED
MODE_MP3_VAL
0x00
RW
0x003C
MODE_MP4
[7:0]
RESERVED
MODE_MP4_VAL
0x00
RW