Datasheet

ADAU1772 Data Sheet
Rev. B | Page 46 of 116
SERIAL DATA INPUT/OUTPUT PORTS
The serial data input and output ports of the ADAU1772 can be set
to accept or transmit data in a 2-channel format or in a 4-channel
or 8-channel TDM stream to interface to external ADCs, DACs,
DSPs, and SOCs. Data is processed in twos complement, MSB
first format. The left-channel data field always precedes the
right-channel data field in the 2-channel streams. In 8-channel
TDM mode, the data channels are output sequentially, starting
with the channel set by the ADC_SDATA0_ST and
ADC_SDATA1_ST bits. The serial modes and the position of
the data in the frame are set in the serial data port (SAI_0,
SAI_1) and serial output control registers
(SOUT_SOURCE_x_x, Address 0x0013 to Address 0x0016).
The serial data clocks do not need to be synchronous with the
ADAU1772 master clock input, but the LRCLK and BCLK must
be synchronous to each other. The LRCLK and BCLK pins are
used to clock both the serial input and output ports. The
ADAU1772 can be set to be either the master or the slave in a
system. Because there is only one set of serial data clocks, the
input and output ports must always both be either master or
slave.
The serial data control registers allow control of the clock polarity
and the data input modes. The valid data formats are I
2
S, left
justified, right justified (24- or 16-bit), PCM, and TDM. In all
modes except for the right justified modes, the serial port inputs
an arbitrary number of bits up to a limit of 24. Extra bits do not
cause an error, but they are truncated internally. The serial port
can operate with an arbitrary number of BCLK transitions in
each LRCLK frame. The LRCLK in TDM mode can be input to
the ADAU1772 either as a 50% duty cycle clock or as a bit-wide
pulse. Table 27 lists the modes in which the serial input/output
port can function. When using low IOVDD (1.8 V) with a high
BCLK rate (12.288 MHz), a sample rate of 192 kHz, or a TDM8
mode operating at a sample rate of 48 kHz, it is recommended
to use the high drive settings on the serial port pins. The high
drive strength effectively speeds up the transition times of the
waveforms, thereby improving the signal integrity of the clock
and data lines. These can be set in the PAD_CONTROL4 register
(Address 0x004C).
Table 27. Serial In/Out Port Master/Slave Mode Capabilities
f
SSD
2-Channel Modes
(I
2
S, Left Justified,
Right Justified)
4-Channel
TDM
8-Channel
TDM
48 kHz Yes Yes Yes
96 kHz Yes Yes No
192 kHz Yes No No
Table 28 describes the proper serial port settings for standard
audio data formats. More information about the settings in this
table can be found in the Serial Port Control 0 and Serial Port
Control 1 registers (Address 0x0032 and Address 0x0033)
descriptions.
TRISTATING UNUSED CHANNELS
Unused outputs can be tristated so that multiple ICs can drive a
single TDM line. This function is available only when the serial
ports of the ADAU1772 are operating in TDM mode. Channels
that are inactive can be set in the SOUT_CONTROL0 register
(Address 0x0034). The tristating of inactive channels is set in
the SAI_1 register (Address 0x0033), which offers the option of
tristating or driving the inactive channel.
In a 32-bit TDM frame with 24-bit data, the eight unused bits
are tristated. Inactive channels are also tristated for the full frame.
Table 28. Serial Port Data Format Settings
Format
LRCLK Polarity
(LR_POL)
LRCLK Type
(LR_MODE)
BCLK Polarity
(BCLKEDGE)
1
MSB Position
(SDATA_FMT)
I
2
S (Figure 86) 0 0 0 00
Left Justified (Figure 87) 1 0 0 01
Right Justified (Figure 88 and Figure 89) 1 0 0 10 or 11
TDM (Figure 90 and Figure 91) 1 0 or 1 0 00
PCM/DSP Short Frame Sync (Figure 92) 1 1 X 00
PCM/DSP Long Frame Sync (Figure 93)
1
0
X
01
1
X = don’t care.
Figure 86. I
2
S Mode—16 Bits to 24 Bits per Channel
MSB LSB
LEFT CHANNEL
MSB LSB
RIGHT CHANNEL
LRCLK
BCLK (64 × f
S
)
I
2
S (24-BIT)
1 2 3 4 24 25 26 32
33 34 35 36 56 57 58
64
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