Datasheet

ADAU1772 Data Sheet
Rev. B | Page 42 of 116
SPI PORT
By default, the ADAU1772 is in I
2
C mode, but it can be put into
SPI control mode by pulling
SS
low three times. This can be easily
accomplished by issuing three SPI writes, which are in turn ignored
by the ADAU1772. The next (fourth) SPI write is then latched
into the SPI port.
The SPI port uses a 4-wire interface—consisting of
SS
, SCLK,
MOSI, and MISO signals—and is always a slave port. The
SS
signal should go low at the beginning of a transaction and high
at the end of a transaction. The SCLK signal latches MOSI on a
low-to-high transition. MISO data is shifted out of the
ADAU1772
on the falling edge of SCLK and should be clocked into a receiving
device, such as a microcontroller, on the SCLK rising edge. The
MOSI signal carries the serial input data, and the MISO signal
is the serial output data. The MISO signal remains tristated until a
read operation is requested. This allows other SPI-compatible
peripherals to share the same readback line.
All SPI transactions have the same basic format shown in Table 23.
A timing diagram is shown in Figure 81 and Figure 82. All data
should be written MSB first. The ADAU1772 can only be taken
out of SPI mode by pulling the
PD
pin low or by powering
down the IC.
Read/
Write
The first byte of an SPI transaction indicates whether the com-
munication is a read or a write with the R/
W
bit. The LSB of this
first byte determines whether the SPI transaction is a read (Logic
Level 1) or a write (Logic Level 0).
Subaddress
The 16-bit subaddress word is decoded into a location in one of
the memories or registers. This subaddress is the location of the
appropriate memory location or register.
Data Bytes
The number of data bytes varies according to the register or
memory being accessed. During a burst mode write, an initial
subaddress is written followed by a continuous sequence of data
for consecutive memory/register locations.
A sample timing diagram for a single-write SPI operation to the
parameter RAM is shown in Figure 81. A sample timing diagram
of a single-read SPI operation is shown in Figure 82. The MISO
pin goes from tristate to being driven at the beginning of Byte 3.
In this example, Byte 0 to Byte 2 contain the addresses and the
R/
W
bit and subsequent bytes carry the data.
Table 23. Generic SPI Word Format
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
1
0000000, R/
W
Register/memory address [15:8] Register/memory address [7:0] data data
1
Continues to end of data.
Figure 81. SPI Write to ADAU1772 Clocking (Single-Write Mode)
Figure 82. SPI Read from ADAU1772 Clocking (Single-Read Mode)
SS
SCLK
MOSI
BYTE 0 BYTE 1 BYTE 2 BYTE 3
10804-074
SS
SCLK
MOSI
MISO
BYTE 0 BYTE 1
DATA DATA DATA
HIGH-ZHIGH-Z
10804-075