Datasheet

Data Sheet ADAU1772
Rev. B | Page 35 of 116
The ADAU1772 has the ability to output PDM control patterns to
configure devices such as the SSM2517. Each pattern is a byte long
and is written with a user defined pattern in the PDM_PATTERN
register (Address 0x0037). The control pattern is enabled and
the output channel selection is configured in the PDM_OUT
register (Address 0x0036). The PDM pattern should not be
changed while the ADAU1772 is outputting the control pattern
to the external device. After the external device is configured,
the control pattern can be disabled. For the SSM2517, the
control pattern must be repeated a minimum of 128 times to
configure the part. Table 14 describes typical control patterns
for the SSM2517.
Table 14. SSM2517 PDM Control Pattern Descriptions
Pattern Control Description
0xAC Power-down. All blocks off except for the PDM
interface. Normal start-up time.
0xD8 Gain optimized for PVDD = 5 V operation. Overrides
GAIN_FS pin setting.
0xD4
Gain optimized for PVDD = 3.6 V operation. Overrides
GAIN_FS pin setting.
0xD2 Gain optimized for PVDD = 2.5 V operation. Overrides
GAIN_FS pin setting.
0xD1 f
S
set to opposite value determined by GAIN_FS pin.
0xE1 Ultralow EMI mode.
0xE2 Half clock cycle pulse mode for power savings.
0xE4 Special 32 kHz/128 × f
S
operation mode.
ASYNCHRONOUS SAMPLE RATE CONVERTERS
The ADAU1772 includes asynchronous sample rate converters
(ASRCs) to enable synchronous full-duplex operation of the
serial ports. Two stereo ASRCs are available for the digital outputs,
and one stereo ASRC is available for the digital input signals.
The ASRCs can convert serial output data from the core rate of
up to 192 kHz back down to less than 8 kHz. All intermediate
frequencies and ratios are also supported.
SIGNAL LEVELS
The ADCs, DACs, and ASRCs have fixed gain settings that should
be considered when configuring the system. These settings were
chosen to maximize performance of the converters and to ensure
that there is 0 dB gain for any signal path from the input of the
ADAU1772 to its output. Therefore, the full-scale level of a signal
in the processing core will be slightly different from a full-scale
level external to the IC.
Input paths, such as through the ADCs and input ASRCs, are
scaled by 0.75, or about −2.5 dB. Output paths, such as through
the DACs or output ASRCs, are scaled by 1.33, or about 2.5 dB.
This is shown in Figure 74.
Figure 74. Signal Level Diagram
Because of this input and output scaling, output signals from
the core should be limited to −2.5 dB full scale to prevent the
DACs and ASRCs from clipping.
ADC
INPUT
ASRCS
–2.5dB
DAC
+2.5dB
–2.5dB
OUTPUT
ASRCS
+2.5dB
CORE
10804-067