Datasheet

Data Sheet ADAU1772
Rev. B | Page 33 of 116
DIGITAL MICROPHONE INPUT
When using a digital microphone connected to the DMIC0_1/MP4
and DMIC2_3/MP5 pins, the DCM_0_1 and DCM_2_3 bits in
Register 0x001D and Register 0x001E must be set to enable the
digital microphone signal paths. The pin functions should also
be set to digital microphone input in the corresponding pin
mode registers (Address 0x003C and Address 0x003D). The
DMIC0/DMIC2 and DMIC1/DMIC3 channels can be swapped
(left/right swap) by writing to the DMIC_SW0 and DMIC_SW1
bits in the ADC_CONTROL2 and ADC_CONTROL3 registers
(Address 0x001D and Address 0x001E). In addition, the micro-
phone polarity can be reversed by setting the DMIC_POLx bit,
which reverses the phase of the incoming audio by 180°.
The digital microphone inputs are clocked from the CLKOUT pin.
The digital microphone data stream must be clocked by this pin
and not by a clock from another source, such as another audio
IC, even if the other clock is of the same frequency as CLKOUT.
The digital microphone signal bypasses the analog input path
and the ADCs and is routed directly into the decimation filters.
The digital microphone and the ADCs share digital filters and,
therefore, both cannot be used simultaneously. The digital micro-
phone inputs are enabled in pairs. The ADAU1772 inputs can be
set for either four analog inputs, four digital microphone inputs, or
two analog inputs and two digital microphone inputs. Figure 72
depicts the digital microphone interface and signal routing.
Figure 72. Digital Microphone Interface Block Diagram
Figure 72 shows two ADMP421 digital microphones connected
to Pin DMIC0_1 of the ADAU1772. These microphones could
also be connected to DMIC2_3 if that signal path is to be used for
digital microphones. If more than two digital microphones are to
be used in a system, then up to two microphones would be con-
nected to both DMIC0_ 1 and DMIC2_3 and the CLKOUT signal
would be fanned out to the clock input of all of the microphones.
ANALOG-TO-DIGITAL CONVERTERS
The ADAU1772 includes four 24-bit Σ-Δ analog-to-digital con-
verters (ADCs) with a selectable sample rate of 192 kHz or 96 kHz.
ADC Full-Scale Level
The full-scale input to the ADCs (0 dBFS) scales linearly with
AVDD. At AV DD = 3.3 V, the full-scale input level is 1 V rms.
Signal levels above the full-scale value cause the ADCs to clip.
Digital ADC Volume Control
The volume setting of each ADC can be digitally attenuated in the
ADCx_VOLUME registers (Address 0x001F to Address 0x0022).
The volume can be set between 0 dB and −95.625 dB in 0.375 dB
steps. The ADC volume can also be digitally muted in the
ADC_CONTROLx registers (Address 0x001B to Address 0x001E).
High-Pass Filter
A high-pass filter is available on the ADC path to remove dc offsets;
this filter can be enabled or disabled using the HP_x_x_EN bits.
At f
S
= 192 kHz, the corner frequency of this high-pass filter can
be set to 1 Hz, 4 Hz, or 8 Hz.
ADAU1772
CLKOUT
DMIC0_1
ADMP421
CLK
V
DD
DATA
L/R SELECT GND
0.1µF
ADMP421
CLK
V
DD
DATA
L/R SELECT GND
0.1µF
1.8V TO 3.3V
10804-065