Datasheet

Data Sheet ADAU1772
Rev. B | Page 3 of 116
Serial Data Output 2/Serial Data Output 3 Input Select
Register ......................................................................................... 66
Serial Data Output 4/Serial Data Output 5 Input Select
Register ......................................................................................... 67
Serial Data Output 6/Serial Data Output 7 Input Select
Register ......................................................................................... 68
ADC_SDATA0/ADC_SDATA1 Channel Select Register ...... 69
Output ASRC0/Output ASRC1 Source Register..................... 70
Output ASRC2/Output ASRC3 Source Register..................... 71
Input ASRC Channel Select Register ........................................ 72
ADC0/ADC1 Control 0 Register .............................................. 73
ADC2/ADC3 Control 0 Register .............................................. 74
ADC0/ADC1 Control 1 Register .............................................. 75
ADC2/ADC3 Control 1 Register .............................................. 76
ADC0 Volume Control Register ............................................... 77
ADC1 Volume Control Register ............................................... 77
ADC2 Volume Control Register ............................................... 78
ADC3 Volume Control Register ............................................... 78
PGA Control 0 Register .............................................................. 79
PGA Control 1 Register .............................................................. 79
PGA Control 2 Register .............................................................. 80
PGA Control 3 Register .............................................................. 81
PGA Slew Control Register ........................................................ 82
PGA 10 dB Gain Boost Register................................................ 83
Input and Output Capacitor Charging Register ..................... 84
DSP Bypass Path Register .......................................................... 85
DSP Bypass Gain for PGA0 Register ........................................ 85
DSP Bypass Gain for PGA1 Register ........................................ 85
MIC_BIAS0_1 Control Register ............................................... 86
DAC Control Register ................................................................ 86
DAC0 Volume Control Register ................................................ 87
DAC1 Volume Control Register ................................................ 87
Headphone Output Mutes Register .......................................... 88
Serial Port Control 0 Register .................................................... 89
Serial Port Control 1 Register .................................................... 90
TDM Output Channel Disable Register .................................. 91
PDM Enable Register ................................................................. 92
PDM Pattern Setting Register ................................................... 93
MP0 Function Setting Register ................................................. 93
MP1 Function Setting Register ................................................. 94
MP2 Function Setting Register ................................................. 95
MP3 Function Setting Register ................................................. 96
MP4 Function Setting Register ................................................. 97
MP5 Function Setting Register ................................................. 98
MP6 Function Setting Register ................................................. 99
Push-Button Volume Settings Register .................................. 100
Push-Button Volume Control Assignment Register ............ 101
Debounce Modes Register ....................................................... 102
Headphone Line Output Select Register ................................ 102
Decimator Power Control Register ........................................ 104
ASRC Interpolator and DAC Modulator Power Control
Register ....................................................................................... 105
Analog Bias Control 0 Register ............................................... 105
Analog Bias Control 1 Register ............................................... 106
Digital Pin Pull-Up Control 0 Register .................................. 107
Digital Pin Pull-Up Control 1 Register .................................. 108
Digital Pin Pull-Down Control 0 Register ............................ 109
Digital Pin Pull-Down Control 1 Register ............................ 110
Digital Pin Drive Strength Control 0 Register ...................... 111
Digital Pin Drive Strength Control 1 Register ...................... 112
Outline Dimensions ...................................................................... 113
Ordering Guide ......................................................................... 113
REVISION HISTORY
12/12—Rev. A to Rev. B
Changes to Figure 90 ...................................................................... 47
8/12—Rev. 0 to Rev. A
Changes to Figure 69 ...................................................................... 31
7/12—Revision 0: Initial Version