Datasheet

Data Sheet ADAU1772
Rev. B | Page 15 of 116
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 9. Pin Configuration
Table 10. Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
1 SDA/MISO D_IO
I
2
C Data (SDA). This pin is a bidirectional open-collector. The line connected to this pin should have
a 2.0 kΩ pull-up resistor.
SPI Data Output (MISO). This SPI data output is used for reading back registers and memory locations.
It is tristated when an SPI read is not active.
2 SCL/SCLK D_IN
I
2
C Clock (SCL). This pin is always an open-collector input when the device is in I
2
C control mode.
When the device is in self-boot mode, this pin is an open-collector output (I
2
C master). The line
connected to this pin should have a 2.0 kΩ pull-up resistor.
SPI Clock (SCLK). This pin can either run continuously or be gated off between SPI transactions.
3 ADDR1/MOSI D_IN I
2
C Address 1 (ADDR1).
SPI Data Input (MOSI).
4
ADDR0/
SS
D_IN
I
2
C Address 0 (ADDR0).
SPI Latch Signal (
SS
). This pin must go low at the beginning of an SPI transaction and high at the
end of a transaction. Each SPI transaction can take a different number of SCLK cycles to complete,
depending on the address and read/write bit that are sent at the beginning of the SPI transaction.
5 SELFBOOT D_IN Self-Boot. Pull this pin up to IOVDD at power-up to enable the self-boot mode.
6 MICBIAS0 A_OUT Bias Voltage for Electret Microphone. Decouple with a 1 µF capacitor.
7 MICBIAS1 A_OUT Bias Voltage for Electret Microphone. Decouple with a 1 µF capacitor.
8 AIN0REF A_IN ADC0 Input Reference. This reference pin should be ac-coupled to ground with a 10 µF capacitor.
9 AIN0 A_IN ADC0 Input.
10 AVDD PWR 1.8 V to 3.3 V Analog Supply. This pin should be decoupled to AGND with a 0.1 μF capacitor.
11 AGND PWR
Analog Ground. The AGND and DGND pins can be tied directly together in a common ground plane.
AGND should be decoupled to AVDD with a 0.1 μF capacitor.
12 CM A_OUT
AVDD/2 V Common-Mode Reference. A 10 μF to 47 μF decoupling capacitor should be connected
between this pin and ground to reduce crosstalk between the ADCs and DACs. The material of the
capacitors is not critical. This pin can be used to bias external analog circuits, as long as they are
not drawing current from CM (for example, the noninverting input of an op amp).
1SDA/MISO
2
SCL/SCLK
3
ADDR1/MOSI
4ADDR0/SS
5SELFBOOT
6MICBIAS0
7MICBIAS1
8AIN0REF
9AIN0
10AVDD
23
AGND
24
AVDD
25
HPOUTRN/LOUTRN
26
HPOUTRP/LOUTRP
27 PD
28 REG_OUT
29 DVDD
30 DGND
22
HPOUTLP/LOUTLP
21 HPOUTLN/LOUTLN
11AGND
12CM
13AIN1REF
15AIN2REF
17AIN3REF
16AIN2
18
AIN3
19AVDD
20AGND
14AIN1
33
DAC_SDATA/MP0
34
ADC_SDATA0/PDMOUT/MP1
35
ADC_SDATA1/CLKOUT/MP6
36
DMIC2_3/MP5
37
DMIC0_1/MP4
38
XTALO
39
XTALI/MCLKIN
40
IOVDD
32
BCLK/MP2
31
LRCLK/MP3
TOP VIEW
(Not to Scale)
ADAU1772
NOTES
1. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE ADAU1772
GROUNDS. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD
BE SOLDERED TO THE GROUND PLANE. SEE THE EXPOSED PAD PCB
DESIGN SECTION FOR MORE INFORMATION.
10804-059