Datasheet

Data Sheet ADAU1772
Rev. B | Page 11 of 116
Limit
Parameter T
MIN
T
MAX
Unit Description
DIGITAL MICROPHONE
t
CF
20 ns Digital microphone clock fall time
t
CR
20 ns Digital microphone clock rise time
t
DS
40 Digital microphone valid data start time
t
DE
0 ns Digital microphone valid data end time
PDM OUTPUT
t
DCF
20 ns PDM clock fall time
t
DCR
20 ns PDM clock rise time
t
DDV
0 30 ns PDM delay time for valid data
Digital Timing Diagrams
Figure 2. Serial Input Port Timing
BCLK
LRCLK
DAC_SDATA
LEFT-JUSTIFIED
MODE
LSB
DAC_SDATA
I
2
S MODE
DAC_SDATA
RIGHT-JUSTIFIED
MODE
t
BH
MSB
MSB – 1
MSB
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
t
LS
t
SS
t
SH
t
SH
t
SS
t
SS
t
SH
t
SS
t
SH
t
LH
t
BL
10804-002