Datasheet

ADAU1772 Data Sheet
Rev. B | Page 10 of 116
DIGITAL TIMING SPECIFICATIONS
−40°C < T
A
< +85°C, IOVDD = 1.71 V to 3.63 V, DVDD = 1.045 V to 1.98 V.
Table 7. Digital Timing
Limit
Parameter T
MIN
T
MAX
Unit Description
MASTER CLOCK
t
MP
37 125 ns MCLKIN period; 8 MHz to 27 MHz input clock using PLL
t
MCLK
77
82
ns
Internal MCLK period; direct MCLK and PLL output divided by 2
SERIAL PORT
t
BL
40 ns BCLK low pulse width (master and slave modes)
t
BH
40 ns BCLK high pulse width (master and slave modes)
t
LS
10 ns LRCLK setup; time to BCLK rising (slave mode)
t
LH
10 ns LRCLK hold; time from BCLK rising (slave mode)
t
SS
5 ns DAC_SDATA setup; time to BCLK rising (master and slave modes)
t
SH
5 ns DAC_SDATA hold; time from BCLK rising (master and slave modes)
t
TS
10 ns BCLK falling to LRCLK timing skew (master mode)
t
SOD
0 34 ns ADC_SDATAx delay; time from BCLK falling (master and slave modes)
t
SOTD
30 ns BCLK falling to ADC_SDATAx driven in TDM tristate mode
t
SOTX
30 ns BCLK falling to ADC_SDATAx tristated in TDM tristate mode
SPI PORT
f
SCLK
6.25 MHz SCLK frequency
t
CCPL
80 ns SCLK pulse width low
t
CCPH
80 ns SCLK pulse width high
t
CLS
5 ns SS setup; time to SCLK rising
t
CLH
100 ns SS hold; time from SCLK rising
t
CLPH
80 ns SS pulse width high
t
CDS
10 ns MOSI setup; time to SCLK rising
t
CDH
10 ns MOSI hold; time from SCLK rising
t
COD
101 ns MISO delay; time from SCLK falling
I
2
C PORT
f
SCL
400 kHz SCL frequency
t
SCLH
0.6 µs SCL high
t
SCLL
1.3 µs SCL low
t
SCS
0.6 µs SCL rise setup time (to SDA falling), relevant for repeated start
condition
t
SCR
250 ns SCL and SDA rise time, C
LOAD
= 400 pF
t
SCH
0.6 µs SCL fall hold time (from SDA falling), relevant for start condition
t
DS
100 ns SDA setup time (to SCL rising)
t
SCF
250 ns SCL fall time; C
LOAD
= 400 pF
t
SDF
250
ns
SDA fall time; C
LOAD
= 400 pF
t
BFT
0.6 µs SCL rise setup time (to SDA rising), relevant for stop condition
I
2
C EEPROM SELF-BOOT
t
SCHE
26 × t
MP
– 70 ns SCL fall hold time (from SDA falling), relevant for start condition; t
MP
is the input clock on the MCLKIN pin
t
SCSE
38 × t
MP
– 70 ns SCL rise setup time (to SDA falling), relevant for repeated start
condition
t
BFTE
70 × t
MP
– 70 ns SCL rise setup time (to SDA rising), relevant for stop condition
t
DSE
6 × t
MP
– 70
ns
Delay from SCL falling to SDA changing
t
BHTE
32 × t
MP
ns SDA rising in self-boot stop condition to SDA falling edge for
external master start condition
MULTIPURPOSE AND POWER-
DOWN PINS
t
GIL
1.5 × 1/f
S
µs MPx input latency; time until high or low value is read by core
t
RLPW
20 ns
PD
low pulse width