Four ADC, Two DAC Low Power Codec with Audio Processor ADAU1772 Data Sheet FEATURES Low power (15 mW for typical noise cancelling solution) I2C and SPI control interfaces, self-boot from I2C EEPROM 7 MP pins supporting dual stereo digital microphone inputs, stereo PDM output, mute, DSP bypass, push-button volume controls, and parameter bank switching Programmable audio processing engine 192 kHz processing path Biquad filters, limiters, volume controls, mixing Low latency, 24-bit ADCs and DACs 102 dB SNR
ADAU1772 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Control Port .................................................................................... 39 Applications ....................................................................................... 1 I2C Port ........................................................................................ 39 General Description .....................................
Data Sheet ADAU1772 Serial Data Output 2/Serial Data Output 3 Input Select Register .........................................................................................66 Headphone Output Mutes Register .......................................... 88 Serial Data Output 4/Serial Data Output 5 Input Select Register .........................................................................................67 Serial Port Control 1 Register....................................................
ADAU1772 Data Sheet SPECIFICATIONS Master clock = core clock = 12.288 MHz, serial input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width = 24 bits, ambient temperature = 25°C, outputs line loaded with 10 kΩ. ANALOG PERFORMANCE SPECIFICATIONS Supply voltages AVDD = IOVDD = 1.8 V, DVDD = 1.1 V, unless otherwise noted. PLL disabled, direct master clock. Table 1.
Data Sheet Parameter Total Harmonic Distortion + Noise Signal-to-Noise Ratio2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter PGA Gain Variation With −12 dB Setting With +35.25 dB Setting PGA Boost PGA Mute Attenuation Interchannel Gain Mismatch Offset Error Gain Error Interchannel Isolation Power Supply Rejection Ratio MICROPHONE BIAS Bias Voltage 0.65 × AVDD 0.
ADAU1772 Parameter Interchannel Gain Mismatch Total Harmonic Distortion + Noise Gain Error Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Signal-to-Noise Ratio2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Interchannel Gain Mismatch Total Harmonic Distortion + Noise 32 Ω load 24 Ω load 16 Ω load Headphone Output Power 32 Ω Load 24 Ω Load 16 Ω Load Gain Error Offset Error Interchannel Isolation Power Supply Rejection Ratio DAC DIFFERENTIAL OUTPUT Full-Scale Out
Data Sheet Parameter Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Signal-to-Noise Ratio2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Interchannel Gain Mismatch Total Harmonic Distortion + Noise 32 Ω Load 24 Ω Load 16 Ω Load Headphone Output Power 32 Ω Load 24 Ω Load 16 Ω Load Gain Error Offset Error Interchannel Isolation Power Supply Rejection Ratio CM REFERENCE Common-Mode Reference Output Common-Mode Source Impedance REGULATOR Line Regulation Load Regulat
ADAU1772 Data Sheet DIGITAL INPUT/OUTPUT SPECIFICATIONS −40°C < TA < +85°C, IOVDD = 3.3 V ± 10% and 1.8 V − 5%/+10%. Table 3. Parameter Input Voltage High (VIH) Input Voltage Low (VIL) Input Leakage Output Voltage High (VOH) with Low Drive Strength Output Voltage High (VOH) with High Drive Strength Output Voltage Low (VOL) with Low Drive Strength Output Voltage Low (VOL) with High Drive Strength Input Capacitance Test Conditions/Comments IOVDD = 3.3 V IOVDD = 1.8 V IOVDD = 3.3 V IOVDD = 1.8 V IOVDD = 3.
Data Sheet ADAU1772 TYPICAL POWER CONSUMPTION Typical active noise cancelling (ANC) settings. Master clock = 12.288 MHz, fS = 192 kHz. On-board regulator enabled. Two analog-todigital converters (ADCs) with PGA enabled and two ADCs configured for line input; no input signal. Two digital-to-analog converters (DACs) configured for differential headphone operation; DAC outputs unloaded. Both MICBIAS0 and MICBIAS1 enabled. ASRCs and pulse density modulated (PDM) modulator disabled.
ADAU1772 Data Sheet DIGITAL TIMING SPECIFICATIONS −40°C < TA < +85°C, IOVDD = 1.71 V to 3.63 V, DVDD = 1.045 V to 1.98 V. Table 7.
Data Sheet ADAU1772 Parameter DIGITAL MICROPHONE tCF tCR tDS tDE PDM OUTPUT tDCF tDCR tDDV Limit TMAX TMIN Unit Description 20 20 ns ns 0 ns Digital microphone clock fall time Digital microphone clock rise time Digital microphone valid data start time Digital microphone valid data end time 20 20 30 ns ns ns PDM clock fall time PDM clock rise time PDM delay time for valid data 40 0 Digital Timing Diagrams tBH BCLK tBL tLH tLS LRCLK tSS DAC_SDATA LEFT-JUSTIFIED MODE MSB MSB – 1 tSH tSS
ADAU1772 Data Sheet tLH tBH tTS BCLK tBL tLS LRCLK tSOD ADC_SDATAx LEFT-JUSTIFIED MODE MSB MSB – 1 tSOD ADC_SDATAx I2S MODE MSB tSOTX tSOTD HIGH-Z ADC_SDATAx W/TRISTATE HIGH-Z MSB LSB tSOD ADC_SDATAx RIGHT-JUSTIFIED MODE LSB MSB 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 10804-003 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) Figure 3. Serial Output Port Timing tCLH tCLS tCLPH tCCPL tCCPH SS SCLK MOSI tCDH 10804-004 tCDS MISO tCOD Figure 4.
Data Sheet ADAU1772 tSCHE tDSE SDA 10804-006 tBHTE SCL tSCSE tBFTE 2 Figure 6. I C Self-Boot Timing CLKOUT tDS tCF tDS tDE tDE DMIC0_1/DMIC2_3 VALID LEFT SAMPLE VALID RIGHT SAMPLE VALID LEFT SAMPLE Figure 7. Digital Microphone Timing tDCF tDCR CLKOUT PDMOUT RIGHT LEFT RIGHT Figure 8. PDM Output Timing Rev.
ADAU1772 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter Power Supply (AVDD, IOVDD) Digital Supply (DVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Rating −0.3 V to +3.63 V −0.3 V to +1.98 V ±20 mA –0.3 V to AVDD + 0.3 V −0.3 to IOVDD + 0.
Data Sheet ADAU1772 40 39 38 37 36 35 34 33 32 31 IOVDD XTALI/MCLKIN XTALO DMIC0_1/MP4 DMIC2_3/MP5 ADC_SDATA1/CLKOUT/MP6 ADC_SDATA0/PDMOUT/MP1 DAC_SDATA/MP0 BCLK/MP2 LRCLK/MP3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADAU1772 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 DGND DVDD REG_OUT PD HPOUTRP/LOUTRP HPOUTRN/LOUTRN AVDD AGND HPOUTLP/LOUTLP HPOUTLN/LOUTLN NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE ADAU1772 GROUNDS.
ADAU1772 Data Sheet Pin No.
Data Sheet ADAU1772 TYPICAL PERFORMANCE CHARACTERISTICS 0.04 120 0.02 110 0 100 90 –0.04 GROUP DELAY (µs) –0.06 –0.08 –0.10 –0.12 –0.14 –0.16 50 40 1k 10k 0 FREQUENCY (Hz) Figure 10. Relative Level vs. Frequency, fS = 48 kHz, Signal Path = AIN0 to DSP (Without Processing) to LOUTLx 4 6 8 10 12 14 16 FREQUENCY (kHz) 18 20 Figure 11. Phase vs.
Data Sheet 50 0 –50 –100 PHASE (Degrees) PHASE (Degrees) –150 –200 –250 –300 –350 –400 –450 –500 –600 0 4 8 12 16 20 24 28 32 36 40 FREQUENCY (kHz) 10804-015 –550 Figure 16. Phase vs. Frequency, 40 kHz Bandwidth, fS = 96 kHz, Signal Path = AIN0 to DSP (Without Processing) to LOUTLx 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 FREQUENCY (kHz) Figure 19. Phase vs.
Data Sheet ADAU1772 0.04 300 0.02 280 260 0 240 220 GROUP DELAY (µs) RELATIVE LEVEL (dB) –0.02 –0.04 –0.06 –0.08 –0.10 –0.12 200 180 160 140 120 100 80 –0.14 60 –0.16 40 –0.18 1k 0 10804-021 100 10k FREQUENCY (Hz) 0 4 6 8 10 12 14 16 18 20 FREQUENCY (kHz) Figure 22. Relative Level vs. Frequency, fS = 48 kHz, Signal Path = AIN0 to ASRC to ADC_SDATA0 Figure 25. Group Delay vs.
Data Sheet PHASE (Degrees) 4 8 12 16 20 24 28 32 36 40 FREQUENCY (kHz) 0 2 300 0 280 0.8 1.0 1.2 1.4 1.6 1.8 2.0 260 240 –4 220 GROUP DELAY (µs) –6 –8 –10 –12 –14 200 180 160 140 120 100 80 –16 60 –18 40 –20 20 100 1k 0 10804-028 –22 10k FREQUENCY (Hz) 0 10 0 5 0 –400 –5 PHASE (Degrees) –200 –600 –800 –1000 –1600 –35 –1800 70 FREQUENCY (kHz) 80 10804-029 –30 60 60 70 80 –20 –25 50 50 –15 –1400 40 40 –10 –1200 30 30 Figure 32.
Data Sheet ADAU1772 0.02 300 0.01 280 260 0 240 220 GROUP DELAY (µs) –0.02 –0.03 –0.04 –0.05 –0.06 180 160 140 120 100 80 –0.07 60 –0.08 40 –0.09 0 10804-033 1k 100 10k FREQUENCY (Hz) 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (kHz) Figure 34. Relative Level vs. Frequency, fS = 48 kHz, Signal Path = DAC_SDATA to ASRC to LOUTLx 10804-036 20 –0.10 Figure 37. Group Delay vs.
PHASE (Degrees) 200 100 0 –100 –200 –300 –400 –500 –600 –700 –800 –900 –1000 –1100 –1200 –1300 –1400 –1500 –1600 –1700 4 8 12 16 20 24 28 32 36 40 FREQUENCY (kHz) 0 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Figure 43. Phase vs. Frequency, 2 kHz Bandwidth, fS = 96 kHz, Signal Path = DAC_SDATA to ASRC to LOUTLx 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 –4.5 –5.0 –5.5 –6.0 –6.5 –7.0 –7.5 –8.
Data Sheet ADAU1772 500 0.020 0.015 450 0.005 400 0 350 GROUP DELAY (µs) RELATIVE LEVEL (dB) 0.010 –0.005 –0.010 –0.015 –0.020 –0.025 –0.030 –0.035 300 250 200 150 100 –0.040 1k 10k FREQUENCY (Hz) Figure 46. Relative Level vs. Frequency, fS = 48 kHz, Signal Path = DAC_SDATA to ASRC to DSP (Without Processing) to ASRC to ADC_SDATA0 2 4 6 8 10 12 14 16 FREQUENCY (kHz) 18 20 Figure 47. Phase vs.
Data Sheet 200 0 –200 PHASE (Degrees) PHASE (Degrees) –400 –600 –800 –1000 –1200 –1400 –1600 –2000 0 4 8 12 16 20 24 28 32 36 40 FREQUENCY (kHz) 10804-051 –1800 Figure 52. Phase vs. Frequency, 40 kHz Bandwidth, fS = 96 kHz, Signal Path = DAC_SDATA to ASRC to DSP (Without Processing) to ASRC to ADC_SDATA0 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 FREQUENCY (kHz) 10804-054 ADAU1772 Figure 55.
Data Sheet ADAU1772 35 2 0 25 MAGNITUDE (dBFS) 20 15 10 –2 –4 –6 –8 5 –6 0 6 12 18 24 30 36 PGA GAIN SETTING (dB) –10 10804-057 0 –12 0 5 10 15 FREQUENCY (kHz) 10804-102 INPUT IMPEDANCE (kΩ) 30 20 Figure 61. Decimation Pass-Band Response, fS = 192 kHz Figure 58. Input Impedance vs. PGA Gain (see the Input Impedance section) 2 0 0 MAGNITUDE (dBFS) –2 –4 –6 –40 –60 –80 –100 –8 0 5 10 15 –120 10804-100 –10 20 FREQUENCY (kHz) 0 Figure 59.
Data Sheet 0 0 –20 –20 MAGNITUDE (dBFS) –40 –60 –80 –60 –80 –100 –120 0 10 20 30 40 50 60 70 FREQUENCY (kHz) 80 90 100 10804-105 –100 Figure 64. Total Interpolation Response, fS = 96 kHz 1 0 –1 –2 0 5 10 15 20 FREQUENCY (kHz) 10804-106 –3 –4 –120 0 1 2 3 4 5 6 7 8 9 FREQUENCY (kHz) Figure 66. Total Interpolation Response, fS = 192 kHz 2 MAGNITUDE (dBFS) –40 Figure 65. Interpolation Pass-Band Response, fS = 192 kHz Rev.
ADAU1772 Data Sheet SYSTEM BLOCK DIAGRAMS DC VOLTAGE SOURCE: 1.8 V TO 3.3 V + 10µF 0.10µF 10µF + 0.10µF 0.10µF 0.10µF 1.0µF LEFT MICROPHONE 2kΩ 2kΩ 37 DMIC0_1/MP4 36 DMIC2_3/MP5 24 AVDD AVDD 10 AVDD 19 IOVDD 40 29 DVDD REG_OUT 28 0.
ADAU1772 Data Sheet THEORY OF OPERATION The ADAU1772 is a low power audio codec with an optimized audio processing core, making it ideal for noise cancelling applications that require high quality audio, low power, small size, and low latency. The four ADC and two DAC channels each have an SNR of at least +96 dB and a THD + N of at least −88 dB. The serial data port is compatible with I2S, left justified, right justified, and TDM modes, with tristating for interfacing to digital audio data.
Data Sheet ADAU1772 SYSTEM CLOCKING AND POWER-UP Control Port Access During Initialization CLOCK INITIALIZATION The ADAU1772 can generate its clocks either from an externally provided clock or from a crystal oscillator. In both cases, the onboard PLL can be used or the clock can be fed directly to the core. When a crystal oscillator is used, it is desirable to use a 12.288 MHz crystal, and the crystal oscillator function must be enabled in the COREN bit (Address 0x0000).
ADAU1772 Data Sheet On power-up, AVDD must be powered up before or at the same time as IOVDD. IOVDD should not be powered up when power is not applied to AVDD. Table 13 lists common fractional PLL parameter settings for 48 kHz sampling rates. When the PLL is used in fractional mode, it is very important that the N/M fraction be kept in the range of 0.1 to 0.9 to ensure correct operation of the PLL. Enabling the PD pin powers down all analog and digital circuits.
Data Sheet ADAU1772 SIGNAL ROUTING AIN0REF PGA AIN0 ADC MODULATOR ADC DECIMATOR AIN1REF PGA AIN1 DMIC0_1/MP4 DMIC2_3/MP5 ADC MODULATOR CORE INPUT SELECTION DIGITAL MICROPHONE INPUTS AIN2REF PGA AIN2 ADC MODULATOR AIN3REF PGA AIN3 HPOUTLP/LOUTLP ADC MODULATOR DAC ADC DECIMATOR AUDIO PROCESSING CORE DAC AND PDM OUTPUT SELECTION ADC DECIMATOR HPOUTLN/LOUTLN HPOUTRP/LOUTRP DAC STEREO PDM MODULATOR HPOUTRN/LOUTRN PDMOUT1 ADC DECIMATOR STEREO INPUT ASRC SERIAL INPUT PORT DUAL STEREO O
ADAU1772 Data Sheet INPUT SIGNAL PATHS ANALOG INPUTS The ADAU1772 can accept both line level and microphone inputs. Each of the four analog input channels can be configured in a single-ended mode or a single-ended with PGA mode. There are also inputs for up to four digital microphones. The analog inputs are biased at AVDD/2. Unused input pins should be connected to the CM pin or ac-coupled to ground. Analog Line Inputs Line level signals can be input on the AINx pins of the analog inputs.
Data Sheet ADAU1772 DIGITAL MICROPHONE INPUT When using a digital microphone connected to the DMIC0_1/MP4 and DMIC2_3/MP5 pins, the DCM_0_1 and DCM_2_3 bits in Register 0x001D and Register 0x001E must be set to enable the digital microphone signal paths. The pin functions should also be set to digital microphone input in the corresponding pin mode registers (Address 0x003C and Address 0x003D).
ADAU1772 Data Sheet OUTPUT SIGNAL PATHS Pop-and-Click Suppression Data from the serial input port can be routed to the core either directly or through a sample rate converter. Data can be routed to the serial output port, the stereo DAC, and the stereo PDM modulator. The analog outputs of the ADAU1772 can be configured as differential or single-ended outputs. The analog output pins are capable of driving headphone or earpiece speakers.
Data Sheet ADAU1772 Table 14. SSM2517 PDM Control Pattern Descriptions Pattern 0xAC 0xD8 0xD4 0xD2 0xD1 0xE1 0xE2 0xE4 Control Description Power-down. All blocks off except for the PDM interface. Normal start-up time. Gain optimized for PVDD = 5 V operation. Overrides GAIN_FS pin setting. Gain optimized for PVDD = 3.6 V operation. Overrides GAIN_FS pin setting. Gain optimized for PVDD = 2.5 V operation. Overrides GAIN_FS pin setting. fS set to opposite value determined by GAIN_FS pin. Ultralow EMI mode.
ADAU1772 Data Sheet SIGNAL PROCESSING The ADAU1772 processing core is optimized for active noise cancelling (ANC) processing. The processing capabilities of the core include biquad filters, limiters, volume controls, and mixing. The core has four inputs and four outputs. The core is controlled with a 10-bit program word, with a maximum of 32 instructions per frame. while the codec is running.
Data Sheet ADAU1772 Table 17.
ADAU1772 Assignment Order 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Data Sheet B0/Max Gain 0x0191 0x0192 0x0193 0x0194 0x0195 0x0196 0x0197 0x0198 0x0199 0x019A 0x019B 0x019C 0x019D 0x019E 0x019F B1/Min Gain 0x01B1 0x01B2 0x01B3 0x01B4 0x01B5 0x01B6 0x01B7 0x01B8 0x01B9 0x01BA 0x01BB 0x01BC 0x01BD 0x01BE 0x01BF Rev.
Data Sheet ADAU1772 CONTROL PORT The ADAU1772 has both a 4-wire SPI control port and a 2-wire I2C bus control port. Each can be used to set the memories and registers. The IC defaults to I2C mode but can be put into SPI control mode by pulling the SS pin low three times. The control port is capable of full read/write operation for all addressable memories and registers. Most signal processing parameters are controlled by writing new values to the parameter memories using the control port.
ADAU1772 Data Sheet R/W bit) MSB first. The device that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This ninth bit is known as an acknowledge bit. All other devices withdraw from the bus at this point and return to the idle condition. The R/W bit determines the direction of the data.
Data Sheet ADAU1772 I2C Read and Write Operations data back to the master. The master then responds every ninth pulse with an acknowledge pulse to the ADAU1772. Figure 77 shows the timing of a single-word write operation. Every ninth clock pulse, the ADAU1772 issues an acknowledge by pulling SDA low. Figure 80 shows the timing of a burst mode read sequence. This figure shows an example where the target read words are two bytes.
ADAU1772 Data Sheet SPI PORT Read/Write By default, the ADAU1772 is in I2C mode, but it can be put into SPI control mode by pulling SS low three times. This can be easily accomplished by issuing three SPI writes, which are in turn ignored by the ADAU1772. The next (fourth) SPI write is then latched into the SPI port. The first byte of an SPI transaction indicates whether the communication is a read or a write with the R/W bit.
Data Sheet ADAU1772 SELF-BOOT CRC The ADAU1772 boots up from an EEPROM over the I2C bus when the SELFBOOT pin is set high at power-up and the PD pin is set high. The state of the SELFBOOT pin is checked only when the ADAU1772 comes out of a reset via the PD pin, and the EEPROM is not used after a self-boot is complete. During booting, ensure that there is a stable DVDD in the system. The PD pin should remain high during the self-boot operation.
ADAU1772 Data Sheet MULTIPURPOSE PINS The ADAU1772 has seven multipurpose (MP) pins that can be used for serial data I/O, clock outputs, and control in a system without a microcontroller. Each pin can be individually set to either its default or MP setting. The functions include pushbutton volume controls, enabling the compressors, parameter bank switching, DSP bypass mode, and muting the outputs.
Data Sheet ADAU1772 DSP BYPASS MODE When DSP bypass mode is enabled, a direct path from the ADC outputs to the DACs is set up to enable bypassing the core processing to listen to environmental sounds. This is useful for listening to someone speaking without having to remove the noise cancelling headphones. The DSP bypass path is enabled by setting an MPx pin low. Figure 84 shows the DSP bypass path disabled, and Figure 85 shows the DSP bypass path enabled by pressing the push-button switch.
ADAU1772 Data Sheet SERIAL DATA INPUT/OUTPUT PORTS The serial data input and output ports of the ADAU1772 can be set to accept or transmit data in a 2-channel format or in a 4-channel or 8-channel TDM stream to interface to external ADCs, DACs, DSPs, and SOCs. Data is processed in twos complement, MSB first format. The left-channel data field always precedes the right-channel data field in the 2-channel streams.
Data Sheet LRCLK ADAU1772 1 2 3 23 24 25 32 33 34 35 55 56 57 64 LJ (24-BIT) MSB LSB MSB 10804-079 BCLK (64 × fS) LSB LEFT CHANNEL RIGHT CHANNEL Figure 87. Left Justified Mode—16 Bits to 24 Bits per Channel LRCLK 1 2 9 10 11 12 32 31 33 34 41 43 42 44 63 64 RJ (24-BIT) MSB MSB LSB 10804-080 BCLK (64 × fS) LSB RIGHT CHANNEL LEFT CHANNEL Figure 88.
ADAU1772 LRCLK Data Sheet 1 2 3 4 16 17 18 19 20 32 33 34 BCLK (64 × fS) LSB MSB LSB MSB 10804-084 PCM (24-BIT) RIGHT CHANNEL LEFT CHANNEL Figure 92. PCM/DSP Mode, 16 Bits per Channel, Short Frame Sync LRCLK 1 2 3 4 16 17 LSB MSB 18 20 19 32 33 34 PCM (24-BIT) MSB LSB RIGHT CHANNEL LEFT CHANNEL Figure 93. PCM/DSP Mode, 16 Bits per Channel, Long Frame Sync Rev.
Data Sheet ADAU1772 APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS EXPOSED PAD PCB DESIGN Each analog and digital power supply pin should be bypassed to its nearest appropriate ground pin with a single 0.1 μF capacitor. The connections to each side of the capacitor should be as short as possible, and the trace should be routed on a single layer with no vias.
ADAU1772 Data Sheet REGISTER SUMMARY Table 29.
Data Sheet Reg 0x003D 0x003E 0x003F 0x0040 Name MODE_MP5 MODE_MP6 PB_VOL_SET PB_VOL_CONV ADAU1772 Bits Bit 7 [7:0] [7:0] [7:0] [7:0] Bit 6 RESERVED RESERVED Bit 4 Bit 3 PB_VOL_INIT_VAL GAINSTEP RAMPSPEED 0x0041 DEBOUNCE_MODE [7:0] 0x0043 OP_STAGE_CTRL [7:0] RESERVED 0x0044 DECIM_PWR_MODES [7:0] DEC_3_EN DEC_2_EN 0x0045 INTERP_PWR_MODES [7:0] 0x0046 BIAS_CONTROL0 [7:0] Bit 5 RESERVED HP_EN_R DEC_1_EN HP_EN_L DEC_0_EN RESERVED HP_IBIAS AFE_IBIAS01 0x0047 BIAS_CONTROL1 0x0048 PAD_CONTROL0 [7:0]
ADAU1772 Data Sheet REGISTER DETAILS CLOCK CONTROL REGISTER Address: 0x0000, Reset: 0x00, Name: CLK_CONTROL This register is used to enable the internal clocks. Table 30. Bit Descriptions for CLK_CONTROL Bits 7 Bit Name PLL_EN Settings 0 1 5 SPK_FLT_DIS 0 1 4 XTAL_DIS 0 1 3 CLKSRC 0 1 2 CC_CDIV 0 1 1 CC_MDIV 0 1 Description Enable PLL. When this bit is set to 0, the PLL is powered down and the PLL output clock is disabled.
Data Sheet Bits 0 Bit Name COREN ADAU1772 Settings 0 1 Description Main clock enable. When COREN = 0, it is only possible to write to this register and the PLL control registers (PLL_CTRL0 to PLL_CTRL5). This control also enables the PLL clock. If using the PLL, do not set COREN = 1 until LOCK in Register PLL_CTRL5 is 1. Note that after COREN is enabled, writing to the parameters is disabled until setting DSP_CLK_EN in the CORE_ENABLE register.
ADAU1772 Data Sheet Table 33. Bit Descriptions for PLL_CTRL2 Bits [7:0] Bit Name N_MSB Settings Description PLL numerator MSB. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x0 Access RW PLL NUMERATOR LSB REGISTER Address: 0x0004, Reset: 0x00, Name: PLL_CTRL3 This register should only be written when PLL_EN = 0 in Register CLK_CONTROL. Table 34. Bit Descriptions for PLL_CTRL3 Bits [7:0] Bit Name N_LSB Settings Description PLL numerator LSB.
Data Sheet Bits [2:1] Bit Name X ADAU1772 Settings 00 01 10 11 0 PLL_TYPE 0 1 Description PLL input clock divide ratio. Pin clock input/1 Pin clock input/2 Pin clock input/3 Pin clock input/4 PLL type. Integer Fractional Reset 0x0 Access RW 0x0 RW Reset 0x0 Access R PLL LOCK FLAG REGISTER Address: 0x0006, Reset: 0x00, Name: PLL_CTRL5 Table 36. Bit Descriptions for PLL_CTRL5 Bits 0 Bit Name LOCK Settings 0 1 Description Flag to indicate if the PLL is locked. This bit is read only.
ADAU1772 Data Sheet Table 37. Bit Descriptions for CLKOUT_SEL Bits [2:0] Bit Name CLKOUT_FREQ Settings 000 001 010 011 100 111 Description CLKOUT pin frequency. Master clock × 2 (24.576 MHz) Master clock (12.288 MHz) Master clock/2 (6.144 MHz) Master clock/4 (3.072 MHz) Master clock/8 (1.536 MHz) Clock output off = 0 Reset 0x0 Access RW Reset 0x0 Access RW 0x0 RW REGULATOR CONTROL REGISTER Address: 0x0008, Reset: 0x00, Name: REGULATOR Table 38.
Data Sheet ADAU1772 CORE CONTROL REGISTER Address: 0x0009, Reset: 0x04, Name: CORE_CONTROL Table 39. Bit Descriptions for CORE_CONTROL Bits 7 Bit Name ZERO_STATE Settings 0 1 [6:5] BANK_SL 00 01 10 11 [2:1] CORE_FS 00 01 10 11 0 CORE_RUN 0 1 Description Zeroes the state of the data memory during bank switching. When switching active parameter banks between two settings, zeroing the state of the bank prevents the new filter settings from being active on old data that is recirculating in filters.
ADAU1772 Data Sheet FILTER ENGINE AND LIMITER CONTROL REGISTER Address: 0x000B, Reset: 0x03, Name: CORE_ENABLE Disabling the limiter only disables the attack operation. The decay operation is always active, so a limiter can be safely disabled while it performs gain adjustments. Table 40. Bit Descriptions for CORE_ENABLE Bits 1 Bit Name LIM_EN Settings 0 1 0 DSP_CLK_EN 0 1 Description Limiter enable.
Data Sheet ADAU1772 DB VALUE REGISTER 0 READ Address: 0x000C, Reset: 0x00, Name: DBREG0 The core can write data to this register, and the data is automatically converted to a level in dB. The most common usage is to determine the rms value of a signal by taking the absolute value, and then performing low-pass filtering and moving the result to the DBREG0 register. Table 41.
ADAU1772 Data Sheet Table 42. Bit Descriptions for DBREG1 Bits [7:0] Bit Name DBVAL1 Settings 00000000 00010000 00100000 00110000 11100000 11110000 11111111 Description DB Value Register 1 read. −96 dB −90 dB −84 dB −78 dB −12 dB −6 dB −0.375 dB Reset 0x00 Access R DB VALUE REGISTER 2 READ Address: 0x000E, Reset: 0x00, Name: DBREG2 The core can write data to this register, and the data is automatically converted to a level in dB.
Data Sheet ADAU1772 CORE CHANNEL 0/CORE CHANNEL 1 INPUT SELECT REGISTER Address: 0x000F, Reset: 0x10, Name: CORE_IN_MUX_0_1 Table 44. Bit Descriptions for CORE_IN_MUX_0_1 Bits [7:4] Bit Name CORE_IN_MUX_SEL_1 Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 [3:0] CORE_IN_MUX_SEL_0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Description Core Input Channel 1 source.
ADAU1772 Data Sheet CORE CHANNEL 2/CORE CHANNEL 3 INPUT SELECT REGISTER Address: 0x0010, Reset: 0x32, Name: CORE_IN_MUX_2_3 Table 45. Bit Descriptions for CORE_IN_MUX_2_3 Bits [7:4] Bit Name CORE_IN_MUX_SEL_3 Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 [3:0] CORE_IN_MUX_SEL_2 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Description Core Input Channel 3 source.
Data Sheet ADAU1772 DAC INPUT SELECT REGISTER Address: 0x0011, Reset: 0x10, Name: DAC_SOURCE_0_1 Table 46. Bit Descriptions for DAC_SOURCE_0_1 Bits [7:4] Bit Name DAC_SOURCE1 Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 [3:0] DAC_SOURCE0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Description DAC1 input source. This setting should not be changed while the core is running. CORE_RUN must be set to 0 for this setting to be updated.
ADAU1772 Data Sheet PDM MODULATOR INPUT SELECT REGISTER Address: 0x0012, Reset: 0x32, Name: PDM_SOURCE_0_1 Table 47. Bit Descriptions for PDM_SOURCE_0_1 Bits [7:4] Bit Name PDM_SOURCE1 Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 [3:0] PDM_SOURCE0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Description PDM Modulator Channel 1 input source.
Data Sheet ADAU1772 SERIAL DATA OUTPUT 0/SERIAL DATA OUTPUT 1 INPUT SELECT REGISTER Address: 0x0013, Reset: 0x54, Name: SOUT_SOURCE_0_1 Table 48. Bit Descriptions for SOUT_SOURCE_0_1 Bits [7:4] Bit Name SOUT_SOURCE1 Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] SOUT_SOURCE0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Description Serial Data Output Channel 1 source select.
ADAU1772 Bits Bit Name Data Sheet Settings 1011 1100 1101 1110 1111 Description Serial Input 3 Serial Input 4 Serial Input 5 Serial Input 6 Serial Input 7 Reset Access Reset 0x7 Access RW 0x6 RW SERIAL DATA OUTPUT 2/SERIAL DATA OUTPUT 3 INPUT SELECT REGISTER Address: 0x0014, Reset: 0x76, Name: SOUT_SOURCE_2_3 Table 49.
Data Sheet Bits Bit Name ADAU1772 Settings 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Reserved Output ASRC Channel 0 Output ASRC Channel 1 Output ASRC Channel 2 Output ASRC Channel 3 Serial Input 0 Serial Input 1 Serial Input 2 Serial Input 3 Serial Input 4 Serial Input 5 Serial Input 6 Serial Input 7 Reset Access Reset 0x5 Access RW SERIAL DATA OUTPUT 4/SERIAL DATA OUTPUT 5 INPUT SELECT REGISTER Address: 0x0015, Reset: 0x54, Name: SOUT_SOURCE_4_5 Table 50.
ADAU1772 Bits Bit Name [3:0] SOUT_SOURCE4 Data Sheet Settings 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Serial Input 4 Serial Input 5 Serial Input 6 Serial Input 7 Serial Data Output Channel 4 source select.
Data Sheet Bits Bit Name [3:0] SOUT_SOURCE6 ADAU1772 Settings 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Output ASRC Channel 0 Output ASRC Channel 1 Output ASRC Channel 2 Output ASRC Channel 3 Serial Input 0 Serial Input 1 Serial Input 2 Serial Input 3 Serial Input 4 Serial Input 5 Serial Input 6 Serial Input 7 Serial Data Output Channel 6 source select.
ADAU1772 Data Sheet Table 52. Bit Descriptions for ADC_SDATA_CH Bits [3:2] Bit Name ADC_SDATA1_ST Settings 00 01 10 11 [1:0] ADC_SDATA0_ST 00 01 10 11 Description SDATA1 output channel output select. Selects the output channel at which ADC_SDATA1 starts to output data. The output port sequentially outputs data following this start channel according to the setting of Bit SAI. Channel 0 Channel 2 Channel 4 Channel 6 SDATA0 output channel output select.
Data Sheet Bits Bit Name [3:0] ASRC_OUT_SOURCE0 ADAU1772 Settings 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Serial Input 3 Serial Input 4 Serial Input 5 Serial Input 6 Serial Input 7 Output ASRC Channel 0 source select.
ADAU1772 Data Sheet Bits Bit Name Settings 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] ASRC_OUT_SOURCE2 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description ADC0 ADC1 ADC2 ADC3 Serial Input 0 Serial Input 1 Serial Input 2 Serial Input 3 Serial Input 4 Serial Input 5 Serial Input 6 Serial Input 7 Output ASRC Channel 2 source select.
Data Sheet Bits Bit Name ADAU1772 Settings 10 11 1 ASRC_OUT_EN 0 1 0 ASRC_IN_EN 0 1 Description Serial Input Port Channel 4/Serial Input Port Channel 5 Serial Input Port Channel 6/Serial Input Port Channel 7 Output ASRC enable. Disabled Enabled Input ASRC enable. Disabled Enabled Reset Access 0x0 RW 0x0 RW Reset 0x1 Access RW 0x1 RW 0x1 RW ADC0/ADC1 CONTROL 0 REGISTER Address: 0x001B, Reset: 0x19, Name: ADC_CONTROL0 Table 56.
ADAU1772 Data Sheet ADC2/ADC3 CONTROL 0 REGISTER Address: 0x001C, Reset: 0x19, Name: ADC_CONTROL1 Table 57. Bit Descriptions for ADC_CONTROL1 Bits 4 Bit Name ADC3_MUTE Settings 0 1 3 ADC2_MUTE 0 1 [1:0] ADC_2_3_FS 00 01 10 11 Description Mute ADC3. Unmuted Muted Mute ADC2. Muting is accomplished by setting the volume control to maximum attenuation. This bit has no effect if volume control is bypassed. Unmuted Muted Sets ADC sample rate. 96 kHz 192 kHz Reserved Reserved Rev.
Data Sheet ADAU1772 ADC0/ADC1 CONTROL 1 REGISTER Address: 0x001D, Reset: 0x00, Name: ADC_CONTROL2 Table 58. Bit Descriptions for ADC_CONTROL2 Bits [6:5] Bit Name HP_0_1_EN Settings 00 01 10 11 4 DMIC_POL0 0 1 3 DMIC_SW0 0 1 2 DCM_0_1 0 1 1 ADC_1_EN 0 1 0 ADC_0_EN 0 1 Description High-pass filter settings. Off 1 Hz 4 Hz 8 Hz Selects microphone polarity. 0 positive, 1 negative 1 positive, 0 negative Digital microphone swap.
ADAU1772 Data Sheet ADC2/ADC3 CONTROL 1 REGISTER Address: 0x001E, Reset: 0x00, Name: ADC_CONTROL3 Table 59. Bit Descriptions for ADC_CONTROL3 Bits [6:5] Bit Name HP_2_3_EN Settings 00 01 10 11 4 DMIC_POL1 0 1 3 DMIC_SW1 0 1 2 DCM_2_3 0 1 1 ADC_3_EN 0 1 0 ADC_2_EN 0 1 Description High-pass filter settings. Off 1 Hz 4 Hz 8 Hz Microphone polarity. 0 positive, 1 negative 1 positive, 0 negative Digital microphone swap.
Data Sheet ADAU1772 ADC0 VOLUME CONTROL REGISTER Address: 0x001F, Reset: 0x00, Name: ADC0_VOLUME When SINC_0_EN is set, the volume starts to ramp from −95.625 dB to the value in this register. The volume ramp time is (number of steps) × 16/fS, where there are 256 steps between 0 dB and −95.625 dB. For example, with fS = 192 kHz, the volume ramps from −95.625 dB to 0 dB in 21 ms. Table 60.
ADAU1772 Data Sheet ADC2 VOLUME CONTROL REGISTER Address: 0x0021, Reset: 0x00, Name: ADC2_VOLUME When SINC_2_EN is set, the volume starts to ramp from −95.625 dB to the value in this register. The volume ramp time is (number of steps) × 16/fS, where there are 256 steps between 0 dB and −95.625 dB. For example, with fS = 192 kHz, the volume ramps from −95.625 dB to 0 dB in 21 ms. Table 62.
Data Sheet ADAU1772 PGA CONTROL 0 REGISTER Address: 0x0023, Reset: 0x40, Name: PGA_CONTROL_0 This register controls the PGA connected to AIN0. Table 64. Bit Descriptions for PGA_CONTROL_0 Bits 7 Bit Name PGA_EN0 Settings 0 1 6 PGA_MUTE0 0 1 [5:0] PGA_GAIN0 000000 000001 010000 111110 111111 Description Select line or microphone input. Note that the PGA inverts the signal going through it. AIN0 used as a single-ended line input. PGA powered down. AIN0 used as a single-ended microphone input.
ADAU1772 Data Sheet Table 65. Bit Descriptions for PGA_CONTROL_1 Bits 7 Bit Name PGA_EN1 Settings 0 1 6 PGA_MUTE1 0 1 [5:0] PGA_GAIN1 000000 000001 010000 111110 111111 Description Select line or microphone input. Note that the PGA inverts the signal going through it. AIN1 used as a single-ended line input. PGA powered down. AIN1 used as a single-ended microphone input. PGA powered up with slewing. Enable PGA1 mute. When PGA is muted, PGA_GAIN1 is ignored. Unmuted Muted Set the gain of PGA1.
Data Sheet ADAU1772 PGA CONTROL 3 REGISTER Address: 0x0026, Reset: 0x40, Name: PGA_CONTROL_3 This register controls the PGA connected to AIN3. Table 67. Bit Descriptions for PGA_CONTROL_3 Bits 7 Bit Name PGA_EN3 Settings 0 1 6 PGA_MUTE3 0 1 [5:0] PGA_GAIN3 000000 000001 010000 111110 111111 Description Select line or microphone input. Note that the PGA inverts the signal going through it. AIN3 used as a single-ended line input. PGA powered down. AIN3 used as a single-ended microphone input.
ADAU1772 Data Sheet PGA SLEW CONTROL REGISTER Address: 0x0027, Reset: 0x00, Name: PGA_STEP_CONTROL If PGA slew is disabled with the SLEW_PDx controls, the SLEW_RATE parameter is ignored for that PGA block. Table 68. Bit Descriptions for PGA_STEP_CONTROL Bits [5:4] Bit Name SLEW_RATE Settings 00 01 10 3 SLEW_PD3 0 1 2 SLEW_PD2 0 1 1 SLEW_PD1 0 1 0 SLEW_PD0 0 1 Description Controls how fast the PGA is slewed when changing gain. 21.5 ms 42.5 ms 85 ms PGA3 slew disable.
Data Sheet ADAU1772 PGA 10 dB GAIN BOOST REGISTER Address: 0x0028, Reset: 0x00, Name: PGA_10DB_BOOST Each PGA can have an additional +10 dB gain added, making the PGA gain range −2 dB to +46 dB. Table 69. Bit Descriptions for PGA_10DB_BOOST Bits 3 Bit Name PGA_3_BOOST Settings 0 1 2 PGA_2_BOOST 0 1 1 PGA_1_BOOST 0 1 0 PGA_0_BOOST 0 1 Description Boost control for PGA3.
ADAU1772 Data Sheet INPUT AND OUTPUT CAPACITOR CHARGING REGISTER Address: 0x0029, Reset: 0x3F, Name: POP_SUPPRESS Table 70. Bit Descriptions for POP_SUPPRESS Bits 5 Bit Name HP_POP_DIS1 Settings 0 1 4 HP_POP_DIS0 0 1 3 PGA_POP_DIS3 0 1 2 PGA_POP_DIS2 0 1 1 PGA_POP_DIS1 0 1 0 PGA_POP_DIS0 0 1 Description Disable pop suppression on Headphone Output 1. Enabled Disabled Disable pop suppression on Headphone Output 0. Enabled Disabled Disable pop suppression on PGA3 input.
Data Sheet ADAU1772 DSP BYPASS PATH REGISTER Address: 0x002A, Reset: 0x00, Name: TALKTHRU Table 71. Bit Descriptions for TALKTHRU Bits [1:0] Bit Name TALKTHRU_PATH Settings 00 01 10 11 Description Signal path when DSP bypass is enabled. No DSP bypass ADC0 to DAC0 ADC1 to DAC1 ADC0 and ADC1 to DAC0 and DAC1 Reset 0x0 Access RW Reset 0x00 Access RW Reset 0x00 Access RW DSP BYPASS GAIN FOR PGA0 REGISTER Address: 0x002B, Reset: 0x00, Name: TALKTHRU_GAIN0 Table 72.
ADAU1772 Data Sheet MIC_BIAS0_1 CONTROL REGISTER Address: 0x002D, Reset: 0x00, Name: MIC_BIAS Table 74. Bit Descriptions for MIC_BIAS Bits 5 Bit Name MIC_EN1 Settings 0 1 4 MIC_EN0 0 1 1 MIC_GAIN1 0 1 0 MIC_GAIN0 0 1 Description MICBIAS1 output enable. Disabled Enabled MICBIAS0 output enable. Disabled Enabled Level of the MICBIAS1 output. 0.9 × AVDD 0.65 × AVDD Level of the MICBIAS0 output. 0.9 × AVDD 0.65 × AVDD DAC CONTROL REGISTER Address: 0x002E, Reset: 0x18, Name: DAC_CONTROL1 Rev.
Data Sheet ADAU1772 Table 75. Bit Descriptions for DAC_CONTROL1 Bits 5 Bit Name DAC_POL Settings 0 1 4 DAC1_MUTE 0 1 3 DAC0_MUTE 0 1 1 DAC1_EN 0 1 0 DAC0_EN 0 1 Description Invert input polarity. Normal Inverted Mute DAC1. Unmuted Muted Mute DAC0. Unmuted Muted Enable DAC1. Disable DAC1 Enable DAC1 Enable DAC0.
ADAU1772 Data Sheet Table 77. Bit Descriptions for DAC1_VOLUME Bits [7:0] Bit Name DAC_1_VOL Settings 00000000 00000001 11111111 Description DAC1 volume setting. 0 dB −0.375 dB −95.625 dB Reset 0x00 Access RW Reset 0x3 Access RW 0x3 RW HEADPHONE OUTPUT MUTES REGISTER Address: 0x0031, Reset: 0x0F, Name: OP_STAGE_MUTES Table 78. Bit Descriptions for OP_STAGE_MUTES Bits [3:2] Bit Name HP_MUTE_R Settings 00 01 10 11 [1:0] HP_MUTE_L 00 01 10 11 Description Mute the right output pins.
Data Sheet ADAU1772 SERIAL PORT CONTROL 0 REGISTER Address: 0x0032, Reset: 0x00, Name: SAI_0 Using 16-bit serial I/O limits device performance. Table 79. Bit Descriptions for SAI_0 Bits [7:6] Bit Name SDATA_FMT Settings 00 01 10 11 [5:4] SAI 00 01 10 11 [3:0] SER_PORT_FS 0000 0001 0010 0011 0100 0101 0110 0111 Description Serial data format.
ADAU1772 Data Sheet SERIAL PORT CONTROL 1 REGISTER Address: 0x0033, Reset: 0x00, Name: SAI_1 Using 16-bit serial I/O limits device performance. Table 80. Bit Descriptions for SAI_1 Bits 7 Bit Name TDM_TS Settings 0 1 6 BCLK_TDMC 0 1 5 LR_MODE 0 1 4 LR_POL 0 1 3 SAI_MSB 0 1 2 BCLKRATE 0 1 1 BCLKEDGE 0 1 0 SAI_MS 0 1 Description Select whether to tristate unused TDM channels or to actively drive these data slots. Unused outputs driven Unused outputs tristated Bit width in TDM mode.
Data Sheet ADAU1772 TDM OUTPUT CHANNEL DISABLE REGISTER Address: 0x0034, Reset: 0x00, Name: SOUT_CONTROL0 This register is for use only in TDM mode. Table 81. Bit Descriptions for SOUT_CONTROL0 Bits 7 Bit Name TDM7_DIS Settings 0 1 6 TDM6_DIS 0 1 5 TDM5_DIS 0 1 4 TDM4_DIS 0 1 3 TDM3_DIS 0 1 2 TDM2_DIS 0 1 1 TDM1_DIS 0 1 0 TDM0_DIS 0 1 Description Disable data in TDM Output Slot 7. Output channel enabled Output channel disabled Disable data in TDM Output Slot 6.
ADAU1772 Data Sheet PDM ENABLE REGISTER Address: 0x0036, Reset: 0x00, Name: PDM_OUT Table 82. Bit Descriptions for PDM_OUT Bits 4 Bit Name PDM_CTRL Settings 0 1 [3:2] PDM_CH 00 01 10 11 [1:0] PDM_EN 00 01 10 11 Description Enable the control pattern in the PDM data stream. Disabled Enabled Selects the channel on which the control patterns are written. These control bits should not be changed while the PDM channel is operating and transmitting audio.
Data Sheet ADAU1772 PDM PATTERN SETTING REGISTER Address: 0x0037, Reset: 0x00, Name: PDM_PATTERN Table 83. Bit Descriptions for PDM_PATTERN Bits [7:0] Bit Name PATTERN Settings Description PDM pattern byte. The PDM pattern byte should not be changed while the PDM channel is operating and transmitting the pattern. Reset 0x00 Access RW Reset 0x00 Access RW MP0 FUNCTION SETTING REGISTER Address: 0x0038, Reset: 0x00, Name: MODE_MP0 Table 84.
ADAU1772 Bits Bit Name Data Sheet Settings 01011 01100 01101 01110 01111 10000 10001 Description A/B bank switch Reserved Reserved Enable compression DSP bypass enable Push-button volume up Push-button volume down Reset Access Reset 0x10 Access RW MP1 FUNCTION SETTING REGISTER Address: 0x0039, Reset: 0x10, Name: MODE_MP1 Table 85.
Data Sheet Bits Bit Name ADAU1772 Settings 10000 10001 10010 Description Push-button volume up Push-button volume down PDM modulator output Reset Access Reset 0x00 Access RW MP2 FUNCTION SETTING REGISTER Address: 0x003A, Reset: 0x00, Name: MODE_MP2 Table 86. Bit Descriptions for MODE_MP2 Bits [4:0] Bit Name MODE_MP2_VAL Settings 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 Description Sets the function of Pin BCLK/MP2.
ADAU1772 Data Sheet MP3 FUNCTION SETTING REGISTER Address: 0x003B, Reset: 0x00, Name: MODE_MP3 Table 87. Bit Descriptions for MODE_MP3 Bits [4:0] Bit Name MODE_MP3_VAL Settings 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 Description Sets the function of Pin LRCLK/MP3.
Data Sheet ADAU1772 MP4 FUNCTION SETTING REGISTER Address: 0x003C, Reset: 0x00, Name: MODE_MP4 Table 88. Bit Descriptions for MODE_MP4 Bits [4:0] Bit Name MODE_MP4_VAL Settings 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 Description Sets the function of Pin DMIC0_1/MP4.
ADAU1772 Data Sheet MP5 FUNCTION SETTING REGISTER Address: 0x003D, Reset: 0x00, Name: MODE_MP5 Table 89. Bit Descriptions for MODE_MP5 Bits [4:0] Bit Name MODE_MP5_VAL Settings 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 Description Sets the function of Pin DMIC2_3/MP5.
Data Sheet ADAU1772 MP6 FUNCTION SETTING REGISTER Address: 0x003E, Reset: 0x11, Name: MODE_MP6 Table 90. Bit Descriptions for MODE_MP6 Bits [4:0] Bit Name MODE_MP6_VAL Settings 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 Description Sets the function of Pin ADC_SDATA1/CLKOUT/MP6.
ADAU1772 Data Sheet PUSH-BUTTON VOLUME SETTINGS REGISTER Address: 0x003F, Reset: 0x00, Name: PB_VOL_SET This register must be written before Bits PB_VOL_CONV_VAL are set to something other than the default value. Otherwise, the pushbutton volume control is initialized to −96 dB. Table 91. Bit Descriptions for PB_VOL_SET Bits [7:3] Bit Name PB_VOL_INIT_VAL Settings 00000 00001 11111 [2:0] HOLD 000 001 010 011 100 101 Description Sets the initial volume of the push-button volume control.
Data Sheet ADAU1772 PUSH-BUTTON VOLUME CONTROL ASSIGNMENT REGISTER Address: 0x0040, Reset: 0x87, Name: PB_VOL_CONV Table 92. Bit Descriptions for PB_VOL_CONV Bits [7:6] Bit Name GAINSTEP Settings 00 01 10 11 [5:3] RAMPSPEED 000 001 010 011 100 101 110 111 [2:0] PB_VOL_CONV_VAL 000 001 010 011 100 101 110 111 Description Sets the gain step for each press of the volume control button. 0.375 dB/press 1.5 dB/press 3.0 dB/press 4.
ADAU1772 Data Sheet DEBOUNCE MODES REGISTER Address: 0x0041, Reset: 0x05, Name: DEBOUNCE_MODE Table 93. Bit Descriptions for DEBOUNCE_MODE Bits [2:0] Bit Name DEBOUNCE Settings 000 001 010 011 100 101 110 111 Description The debounce time setting for the MPx inputs. Debounce 300 µs Debounce 600 µs Debounce 900 µs Debounce 5 ms Debounce 10 ms Debounce 20 ms Debounce 40 ms No debounce HEADPHONE LINE OUTPUT SELECT REGISTER Address: 0x0043, Reset: 0x0F, Name: OP_STAGE_CTRL Rev.
Data Sheet ADAU1772 Table 94. Bit Descriptions for OP_STAGE_CTRL Bits 5 Bit Name HP_EN_R Settings 0 1 4 HP_EN_L 0 1 [3:2] HP_PDN_R 00 01 10 11 [1:0] HP_PDN_L 00 01 10 11 Description Sets the right channel in line output or headphone mode. Right output in line output mode Right output in headphone mode Sets the left channel in line output or headphone mode. Left output in line output mode Left output in headphone output mode Output stage power control.
ADAU1772 Data Sheet DECIMATOR POWER CONTROL REGISTER Address: 0x0044, Reset: 0x00, Name: DECIM_PWR_MODES These bits enable clocks to the digital filters and ASRC decimator filters of the ADCs. These bits must be enabled for all channels that will be used in the design. To use the ADCs, these SINC_x_EN bits must be enabled along with the appropriate ADC_x_EN bits in the ADC_CONTROL2 and ADC_CONTROL3 registers.
Data Sheet ADAU1772 ASRC INTERPOLATOR AND DAC MODULATOR POWER CONTROL REGISTER Address: 0x0045, Reset: 0x00, Name: INTERP_PWR_MODES Table 96. Bit Descriptions for INTERP_PWR_MODES Bits 3 Bit Name MOD_1_EN Settings 0 1 2 MOD_0_EN 0 1 1 INT_1_EN 0 1 0 INT_0_EN 0 1 Description DAC Modulator 1 enable. Powered down Powered up DAC Modulator 0 enable. Powered down Powered up ASRC Interpolator 1 enable. Powered down Powered up ASRC Interpolator 0 enable.
ADAU1772 Data Sheet Table 97. Bit Descriptions for BIAS_CONTROL0 Bits [7:6] Bit Name HP_IBIAS Settings 00 01 10 11 [5:4] AFE_IBIAS01 00 01 10 11 [3:2] ADC_IBIAS23 00 01 10 11 [1:0] ADC_IBIAS01 00 01 10 11 Description Headphone output bias current setting. Higher bias currents result in higher performance. Normal operation (default) Extreme power saving Enhanced performance Power saving Analog Front-End 0 and Analog Front-End 1 bias current setting.
Data Sheet Bits [5:4] Bit Name AFE_IBIAS23 ADAU1772 Settings 00 01 10 11 [3:2] MIC_IBIAS 00 01 10 11 [1:0] DAC_IBIAS 00 01 10 11 Description Analog Front-End 2 and Analog Front-End 3 bias current setting. Higher bias currents result in higher performance. Normal operation (default) Extreme power saving Enhanced performance Power saving Microphone input bias current setting. Higher bias currents result in higher performance.
ADAU1772 Bits 3 Bit Name BCLK_PU Data Sheet Settings 0 1 2 ADC_SDATA1_PU 0 1 1 ADC_SDATA0_PU 0 1 0 DAC_SDATA_PU 0 1 Description Pull-up disable. Pull-up enabled Pull-up disabled Pull-up disable. Pull-up enabled Pull-up disabled Pull-up disable. Pull-up enabled Pull-up disabled Pull-up disable.
Data Sheet ADAU1772 DIGITAL PIN PULL-DOWN CONTROL 0 REGISTER Address: 0x004A, Reset: 0x00, Name: PAD_CONTROL2 Controls the behavior of the pad. Possible to enable pull-down. Table 101. Bit Descriptions for PAD_CONTROL2 Bits 6 Bit Name DMIC2_3_PD Settings 0 1 5 DMIC0_1_PD 0 1 4 LRCLK_PD 0 1 3 BCLK_PD 0 1 2 ADC_SDATA1_PD 0 1 1 ADC_SDATA0_PD 0 1 0 DAC_SDATA_PD 0 1 Description Pull-down enable. Pull-down disabled Pull-down enabled Pull-down enable.
ADAU1772 Data Sheet DIGITAL PIN PULL-DOWN CONTROL 1 REGISTER Address: 0x004B, Reset: 0x00, Name: PAD_CONTROL3 Controls the behavior of the pad. Possible to enable pull-down. Table 102. Bit Descriptions for PAD_CONTROL3 Bits 4 Bit Name SELFBOOT_PD Settings 0 1 3 SCL_PD 0 1 2 SDA_PD 0 1 1 ADDR1_PD 0 1 0 ADDR0_PD 0 1 Description Pull-down enable. Pull-down disabled Pull-down enabled Pull-down enable. Pull-down disabled Pull-down enabled Pull-down enable.
Data Sheet ADAU1772 DIGITAL PIN DRIVE STRENGTH CONTROL 0 REGISTER Address: 0x004C, Reset: 0x00, Name: PAD_CONTROL4 Table 103. Bit Descriptions for PAD_CONTROL4 Bits 4 Bit Name LRCLK_DRV Settings 0 1 3 BCLK_DRV 0 1 2 ADC_SDATA1_DRV 0 1 1 ADC_SDATA0_DRV 0 1 Description Drive strength control. Low drive strength High drive strength Drive strength control. Low drive strength High drive strength Drive strength control. Low drive strength High drive strength Drive strength control.
ADAU1772 Data Sheet DIGITAL PIN DRIVE STRENGTH CONTROL 1 REGISTER Address: 0x004D, Reset: 0x00, Name: PAD_CONTROL5 Table 104. Bit Descriptions for PAD_CONTROL5 Bits 3 Bit Name SCL_DRV Settings 0 1 2 SDA_DRV 0 1 Description Drive strength control. Low drive strength High drive strength Drive strength control. Low drive strength High drive strength Rev.
Data Sheet ADAU1772 OUTLINE DIMENSIONS 6.10 6.00 SQ 5.90 31 40 30 0.50 BSC 1 0.80 0.75 0.70 0.45 0.40 0.35 10 11 20 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 4.45 4.30 SQ 4.25 EXPOSED PAD 21 TOP VIEW PIN 1 INDICATOR BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WJJD. 05-06-2011-A PIN 1 INDICATOR 0.30 0.23 0.18 Figure 97.
ADAU1772 Data Sheet NOTES Rev.
Data Sheet ADAU1772 NOTES Rev.
ADAU1772 Data Sheet NOTES ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10804-0-12/12(B) Rev.
