Datasheet

ADAU1761
Rev. C | Page 85 of 92
R63: DSP Slew Modes, 16,631 (0x40F7)
The DSP slew modes register sets the slew source for each output. The slew source can be either the DSP (digital slew) or the codec (analog
slew). When these bits are set to Logic 0, the codec provides volume slew according to the ASLEW[1:0] bits in Register R34 (playback
pop/click suppression register, Address 0x4028). When these bits are set to Logic 1, the slew is provided and defined by the DSP program,
disabling the codec volume slew.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved MOSLW
ROSLW LOSLW
RHPSLW LHPSLW
Table 88. DSP Slew Modes Register
Bits Bit Name Description
4 MOSLW Mono output slew generation.
0 = codec (default).
1 = DSP.
3 ROSLW Line output right slew generation.
0 = codec (default).
1 = DSP.
2 LOSLW Line output left slew generation.
0 = codec (default).
1 = DSP.
1 RHPSLW Headphone right slew generation.
0 = codec (default).
1 = DSP.
0 LHPSLW Headphone left slew generation.
0 = codec (default).
1 = DSP.
R64: Serial Port Sampling Rate, 16,632 (0x40F8)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved
SPSR[2:0]
Table 89. Serial Port Sampling Rate Register
Bits Bit Name Description
[2:0] SPSR[2:0]
Serial port sampling rate. The serial port sampling rate is a ratio of the base sampling rate, f
S
. The base sampling
rate is determined by the operating frequency of the core clock. For most applications, the serial port sampling
rate should equal the converter sampling rate (set using the CONVSR[2:0] bits in Register R17) and the DSP sampling
rate (set using the DSPSR[3:0] bits in Register R57).
Setting Sampling Rate Base Sampling Rate (f
S
= 48 kHz)
000 f
S
48 kHz, base (default)
001 f
S
/6 8 kHz
010 f
S
/4 12 kHz
011 f
S
/3 16 kHz
100 f
S
/2 24 kHz
101 f
S
/1.5 32 kHz
110 f
S
/0.5 96 kHz
111 Reserved