Datasheet

ADAU1761
Rev. C | Page 82 of 92
R52 to R56: Watchdog Registers, 16,592 to 16,596 (0x40D0 to 0x40D4)
A program counter watchdog is used when the core does block processing (which can span several samples). The watchdog flags an error
if the program counter reaches a specific 24-bit value (ranging from 0x000000 to 0xFFFFFF) that is set in the register map. This value
consists of three consecutive 8-bit register locations. The error flag sends a high signal to one of the GPIO pins. The watchdog function
must be enabled by setting the DOGEN bit high in Register R52 (Address 0x40D0).
The watchdog error bit (DOGER) is the 1-bit watchdog error flag that can be sent to a GPIO pin, as described in Table 79. This error flag
can connect, for example, to an interrupt pin on a microcontroller in the system. The flag is reset when the DOGEN bit goes low. This
flag can also be read back over the control port from Register R56 (Address 0x40D4).
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x40D0 Reserved DOGEN
0x40D1 DOG[23:16]
0x40D2 DOG[15:8]
0x40D3 DOG[7:0]
0x40D4 Reserved DOGER
Table 81. Watchdog Registers
Address
Register
Decimal
Bit Name
Hex
Description
R52 16,592 0x40D0 DOGEN Watchdog enable bit.
0 = disabled (default).
1 = enabled.
R53 16,593 0x40D1 DOG[23:16] Watchdog value, Bits[23:16] (MSB).
R54 16,594 0x40D2 DOG[15:8] Watchdog value, Bits[15:8].
R55 16,595 0x40D3 DOG[7:0] Watchdog value, Bits[7:0].
DOG[23:16] DOG[15:8] DOG[7:0] Hex Value
00000000 00000000 00000000 0x000000 (default)
… … … …
11111111 11111111 11111111
0xFFFFFF
R56 16,596 0x40D4 DOGER Watchdog error (read-only bit).
0 = no error (default).
1 = error.
R57: DSP Sampling Rate Setting, 16,619 (0x40EB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved DSPSR[3:0]
Table 82. DSP Sampling Rate Setting Register
Bits Bit Name Description
[3:0] DSPSR[3:0]
SigmaDSP core sampling rate. The DSP sampling rate is a ratio of the base sampling rate, f
S
. The base sampling rate
is determined by the operating frequency of the core clock. For most applications, the SigmaDSP core sampling
rate should equal the converter sampling rate (set using the CONVSR[2:0] bits in Register R17) and the serial
port sampling rate (set using the SPSR[2:0] bits in Register R64).
Setting Sampling Rate Base Sampling Rate (f
S
= 48 kHz)
0000 f
S
/0.5 96 kHz, base
0001 f
S
48 kHz (default)
0010 f
S
/1.5 32 kHz
0011 f
S
/2 24 kHz
0100 f
S
/3 16 kHz
0101 f
S
/4 12 kHz
0110 f
S
/6 8 kHz
0111 Serial input data rate
1000 Serial output data rate
1111 None