Datasheet

ADAU1761
Rev. C | Page 65 of 92
R17: Converter Control 0, 16,407 (0x4017)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved
DAPAIR[1:0]
DAOSR ADOSR
CONVSR[2:0]
Table 51. Converter Control 0 Register
Bits Bit Name Description
[6:5] DAPAIR[1:0] On-chip DAC serial data selection in TDM 4 or TDM 8 mode.
Setting Pair
00 First pair (default)
01 Second pair
10
Third pair
11
Fourth pair
4 DAOSR DAC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.
0 = 128× (default).
1 = 64×.
3 ADOSR ADC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.
0 = 128× (default).
1 = 64×.
[2:0] CONVSR[2:0]
Converter sampling rate. The ADCs and DACs operate at the sampling rate set in this register. The converter rate
selected is a ratio of the base sampling rate, f
S
. The base sampling rate is determined by the operating frequency
of the core clock.
Setting Sampling Rate Base Sampling Rate (f
S
= 48 kHz)
000 f
S
48 kHz, base (default)
001 f
S
/6 8 kHz
010 f
S
/4 12 kHz
011 f
S
/3 16 kHz
100 f
S
/2 24 kHz
101 f
S
/1.5 32 kHz
110 f
S
/0.5 96 kHz
111 Reserved
R18: Converter Control 1, 16,408 (0x4018)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved ADPAIR[1:0]
Table 52. Converter Control 1 Register
Bits Bit Name Description
[1:0] ADPAIR[1:0] On-chip ADC serial data selection in TDM 4 or TDM 8 mode.
Setting Pair
00 First pair (default)
01 Second pair
10
Third pair
11 Fourth pair