Datasheet

ADAU1761
Rev. C | Page 64 of 92
R16: Serial Port Control 1, 16,406 (0x4016)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BPF[2:0]
ADTDM DATDM MSBP
LRDEL[1:0]
Table 50. Serial Port Control 1 Register
Bits Bit Name Description
[7:5] BPF[2:0] Number of bit clock cycles per LRCLK audio frame.
Setting Bit Clock Cycles
000 64 (default)
001 Reserved
010
48
011
128
100
256
101
Reserved
110
Reserved
111
Reserved
4 ADTDM ADC serial audio data channel position in TDM mode.
0 = left first (default).
1 = right first.
3 DATDM DAC serial audio data channel position in TDM mode.
0 = left first (default).
1 = right first.
2 MSBP MSB position in the LRCLK frame.
0 = MSB first (default).
1 = LSB first.
[1:0] LRDEL[1:0] Data delay from LRCLK edge (in BCLK units).
Setting Delay (Bit Clock Cycles)
00 1 (default)
01 0
10
8
11 16