Datasheet

ADAU1761
Rev. C | Page 53 of 92
R1: PLL Control, 16,386 (0x4002)
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 M[15:8]
1 M[7:0]
2 N[15:8]
3 N[7:0]
4 Reserved R[3:0] X[1:0] Type
5 Reserved Lock PLLEN
Table 35. PLL Control Register
Byte Bits Bit Name Description
0 [7:0] M[15:8] PLL denominator MSB. This value is concatenated with M[7:0] to make up a 16-bit number.
1 [7:0] M[7:0] PLL denominator LSB. This value is concatenated with M[15:8] to make up a 16-bit number.
M[15:8] (MSB) M[7:0] (LSB) Value of M
00000000 00000000 0
… … …
00000000 11111101 253 (default)
… … …
11111111 11111111 65,535
2 [7:0] N[15:8] PLL numerator MSB. This value is concatenated with N[7:0] to make up a 16-bit number.
3 [7:0] N[7:0] PLL numerator LSB. This value is concatenated with N[15:8] to make up a 16-bit number.
N[15:8] (MSB) N[7:0] (LSB) Value of N
00000000 00000000 0
… … …
00000000 00001100 12 (default)
… … …
11111111 11111111 65,535
4 [6:3] R[3:0] PLL integer setting.
Setting Value of R
0010 2 (default)
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
4 [2:1] X[1:0] PLL input clock divider.
Setting Value of X
00 1 (default)
01 2
10 3
11 4
4 0 Type Type of PLL. When set to integer mode, the values of M and N are ignored.
0 = integer (default).
1 = fractional.
5 1 Lock PLL lock. This read-only bit is flagged when the PLL has finished locking.
0 = PLL unlocked (default).
1 = PLL locked.
5 0 PLLEN
PLL enable.
0 = PLL disabled (default).
1 = PLL enabled.