Datasheet
ADAU1761
Rev. C | Page 52 of 92
Reg Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default
R47 0x40C4 CRC enable Reserved CRCEN 00000000
R48 0x40C6 GPIO0 pin control Reserved GPIO0[3:0] 00000000
R49 0x40C7 GPIO1 pin control Reserved GPIO1[3:0] 00000000
R50 0x40C8 GPIO2 pin control Reserved GPIO2[3:0] 00000000
R51 0x40C9 GPIO3 pin control Reserved GPIO3[3:0] 00000000
R52 0x40D0 Watchdog enable Reserved DOGEN 00000000
R53 0x40D1 DOG[23:16] 00000000
R54 0x40D2 DOG[15:8] 00000000
R55 0x40D3
Watchdog value
DOG[7:0] 00000000
R56 0x40D4 Watchdog error Reserved DOGER 00000000
R57 0x40EB DSP sampling rate
setting
Reserved DSPSR[3:0] 00000001
R58 0x40F2 Serial input route
control
Reserved SINRT[3:0] 00000000
R59 0x40F3 Serial output route
control
Reserved SOUTRT[3:0] 00000000
R60 0x40F4 Serial data/GPIO
pin configuration
Reserved LRGP3 BGP2 SDOGP1 SDIGP0 00000000
R61 0x40F5 DSP enable Reserved DSPEN 00000000
R62 0x40F6 DSP run Reserved DSPRUN 00000000
R63 0x40F7 DSP slew modes Reserved MOSLW ROSLW LOSLW RHPSLW LHPSLW 00000000
R64 0x40F8 Serial port
sampling rate
Reserved SPSR[2:0] 00000000
R65 0x40F9 Clock Enable 0 Reserved SLEWPD ALCPD DECPD SOUTPD INTPD SINPD SPPD 00000000
R66 0x40FA Clock Enable 1 Reserved CLK1 CLK0 00000000
CONTROL REGISTER DETAILS
All registers except for the PLL control register are 1-byte write and read registers.
R0: Clock Control, 16,384 (0x4000)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved CLKSRC INFREQ[1:0] COREN
Table 34. Clock Control Register
Bits Bit Name Description
3 CLKSRC
Clock source select.
0 = direct from MCLK pin (default).
1 = PLL clock.
[2:1] INFREQ[1:0]
Input clock frequency. Sets the core clock rate that generates the core clock. If the PLL is used, this value is
automatically set to 1024 × f
S
.
Setting Input Clock Frequency
00 256 × f
S
(default)
01 512 × f
S
10 768 × f
S
11 1024 × f
S
0 COREN
Core clock enable. Only the R0 and R1 registers can be accessed when this bit is set to 0 (core clock disabled).
0 = core clock disabled (default).
1 = core clock enabled.