Datasheet

ADAU1761
Rev. C | Page 43 of 92
LRCL
K
BCLK
SDATA MSB
LEFT CHANNEL
LSB
MSB
RIGHT CHANNEL
LSB
1/f
S
07680-040
Figure 58. I
2
S Mode—16 Bits to 24 Bits per Channel
LRCLK
BCLK
SDATA
LEFT CHANNEL
MSB LSB MSB
RIGHT CHANNEL
LSB
1/ f
S
0
7680-041
Figure 59. Left-Justified Mode—16 Bits to 24 Bits per Channel
LRCLK
BCLK
SDATA
LEFT CHANNEL
MSB LSB MSB
RIGHT CHANNEL
LSB
1/ f
S
07680-042
Figure 60. Right-Justified Mode—16 Bits to 24 Bits per Channel
LRCLK
BCLK
S
DAT
A
SLOT 0 SLOT 3 SLOT 4
32 BCLKs
MSB MSB – 1 MSB – 2
256 BCLKs
SLOT 1 SLOT 2 SLOT 5 SLOT 6 SLOT 7
LRCLK
BCLK
SDATA
07680-043
Figure 61. TDM 8 Mode
LRCLK
SLOT 0 SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7
CH
0
BCLK
SDATA
MSB TDM
CH
8
32
BCLKs
MSB TDM
07680-044
Figure 62. TDM 8 Mode with Pulse Word Clock