Datasheet

ADAU1761
Rev. C | Page 33 of 92
INPUT
GAIN
OUTPUT
DECAY
TIME
ATTACK
TIME
HOLD
TIME
07680-025
Figure 38. Basic ALC Operation
INPUT LEVEL (dB)
TARGET
MIN PGA
GAIN POINT
MAX GAIN = 18dB
MAX GAIN = 24dB
MAX GAIN = 30dB
OUTPUT LEVEL (dB)
0
7680-026
Figure 39. Effect of Varying the Maximum Gain Parameter
NOISE GATE FUNCTION
When using the ALC, one potential problem is that for small
input signals, the PGA gain can become very large. A side effect
of this is that the noise is amplified along with the signal of
interest. To avoid this situation, the ADAU1761 noise gate can
be used. The noise gate cuts off the ADC output when its signal
level is below a set threshold. The noise gate is controlled using
the following parameters in the ALC Control 3 register
(Address 0x4014):
• NGTYP[1:0]: The noise gate type is set to one of four
modes by writing to the NGTYP[1:0] bits.
• NGEN: The noise gate function is enabled by writing to the
NGEN bit.
• NGTHR[4:0]: The threshold for muting the output is set by
writing to the NGTHR[4:0] bits.
One common problem with noise gate functions is chatter,
where a small signal that is close to the noise gate threshold
varies in amplitude, causing the noise gate function to open and
close rapidly. This causes an unpleasant sound.
To reduce this effect, the noise gate in the ADAU1761 uses a
combination of a timeout period and hysteresis. The timeout
period is set to 250 ms, so the signal must consistently be below
the threshold for 250 ms before the noise gate operates.
Hysteresis is used so that the threshold for coming out of the
mute state is 6 dB higher than the threshold for going into the
mute state. There are four operating modes for the noise gate.
Noise Gate Mode 0 (see Figure 40) is selected by setting the
NGTYP[1:0] bits to 00. In this mode, the current state of the
PGA gain is held at its current state when the noise gate logic is
activated. This prevents a large increase in background noise
during periods of silence. When using this mode, it is advisable
to use a relatively slow decay time. This is because the noise gate
takes at least 250 ms to activate, and if the PGA gain has already
increased to a large value during this time, the value at which
the gain is held will be large.
INPUT
ANALOG
GAIN
DIGITAL
MUTE
GAIN HELD
THRESHOLD
OUTPUT
INTERNAL
NOISE GATE
ENABLE SIGNAL
250ms
07680-027
Figure 40. Noise Gate Mode 0 (PGA Gain Hold)
Noise Gate Mode 1 (see Figure 41) is selected by setting the
NGTYP[1:0] bits to 01. In this mode, the ADAU1761 does a
simple digital mute of the ADC output. Although this mode
completely eliminates any background noise, the effect of an
abrupt mute may not be pleasant to the ear.
THRESHOLD
INPUT
ANALOG
GAIN
DIGITAL
MUTE
OUTPUT
INTERNAL
NOISE GATE
ENABLE SIGNAL
250ms
07680-028
Figure 41. Noise Gate Mode 1 (Digital Mute)