Datasheet

ADAU1761
Rev. C | Page 28 of 92
Bits Bit Name Description
[10:9] X[1:0] PLL input clock divider
00: X = 1 (default)
01: X = 2
10: X = 3
11: X = 4
8 Type PLL operation mode
0: Integer (default)
1: Fractional
1 Lock PLL lock (read-only bit)
0: PLL unlocked (default)
1: PLL locked
0 PLLEN PLL enable
0: PLL disabled (default)
1: PLL enabled
Table 16. Fractional PLL Parameter Settings for f
S
= 44.1 kHz (PLL Output = 45.1584 MHz = 1024 × f
S
)
MCLK Input (MHz) Input Divider (X) Integer (R) Denominator (M) Numerator (N) R2: PLL Control Setting (Hex)
8 1 5 625 403 0x0271 0193 2901
12 1 3 625 477 0x0271 01DD 1901
13 1 3 8125 3849 0x1FBD 0F09 1901
14.4 2 6 125 34 0x007D 0022 3301
19.2 2 4 125 88 0x007D 0058 2301
19.68 2 4 1025 604 0x0401 025C 2301
19.8 2 4 1375 772 0x055F 0304 2301
24 2 3 625 477 0x0271 01DD 1B01
26 2 3 8125 3849 0x1FBD 0F09 1B01
27 2 3 1875 647 0x0753 0287 1B01
Table 17. Fractional PLL Parameter Settings for f
S
= 48 kHz (PLL Output = 49.152 MHz = 1024 × f
S
)
MCLK Input (MHz) Input Divider (X) Integer (R) Denominator (M) Numerator (N) R2: PLL Control Setting (Hex)
8 1 6 125 18 0x007D 0012 3101
12 1 4 125 12 0x007D 000C 2101
13 1 3 1625 1269 0x0659 04F5 1901
14.4 2 6 75 62 0x004B 003E 3301
19.2 2 5 25 3 0x0019 0003 2B01
19.68 2 4 205 204 0x00CD 00CC 2301
19.8 2 4 825 796 0x0339 031C 2301
24 2 4 125 12 0x007D 000C 2301
26 2 3 1625 1269 0x0659 04F5 1B01
27 2 3 1125 721 0x0465 02D1 1B01
Table 18. Integer PLL Parameter Settings for f
S
= 48 kHz (PLL Output = 49.152 MHz = 1024 × f
S
)
MCLK Input (MHz) Input Divider (X) Integer (R) Denominator (M) Numerator (N) R2: PLL Control Setting (Hex)
1
12.288 1 4 Don’t care Don’t care 0xXXXX XXXX 2001
24.576 1 2 Don’t care Don’t care 0xXXXX XXXX 1001
1
X = don’t care.