Datasheet

ADAU1761
Rev. C | Page 26 of 92
CLOCKING AND SAMPLING RATES
MCLK
INFREQ[1:0]
SERIAL
DATA INPUT/
OUTPUT PORT
ADCs
DACs
÷ X
× (R + N/M)
R1: PLL CONTROL REGISTER
CLKSRC
R0: CLOCK
CONTROL REGISTER
CORE
CLOCK
R17: CONVERTER
SAMPLING RATE
256 × f
S
, 512 × f
S
,
768 ×
f
S
, 1024 × f
S
CONVSR[2:0]
f
S
/0.5, 1, 1.5, 2, 3, 4, 6
R57: DSP SAMPLIN
G
RATE SETTING
DSPSR[3:0]
f
S
/0.5, 1, 1.5, 2, 3, 4, 6
R64: SERIAL PORT
SAMPLING RATE
SPSR[2:0]
f
S
/0.5, 1, 1.5, 2, 3, 4, 6
ADC_SDATA/GPIO1
DAC_SDATA/GPIO0
LRCLK/GPIO3
BCLK/GPIO2
07680-020
Figure 30. Clock Tree Diagram
CORE CLOCK
Clocks for the converters, the serial ports, and the DSP are
derived from the core clock. The core clock can be derived
directly from MCLK or it can be generated by the PLL. The
CLKSRC bit (Bit 3 in Register R0, Address 0x4000) determines
the clock source.
The INFREQ[1:0] bits should be set according to the expected
input clock rate selected by CLKSRC; this value also determines
the core clock rate and the base sampling frequency, f
S
.
For example, if the input to CLKSRC = 49.152 MHz (from
PLL), then
INFREQ[1:0] = 1024 × f
S
f
S
= 49.152 MHz/1024 = 48 kHz
The PLL output clock rate is always 1024 × f
S
, and the clock
control register automatically sets the INFREQ[1:0] bits to
1024 × f
S
when using the PLL. When using a direct clock, the
INFREQ[1:0] frequency should be set according to the MCLK
pin clock rate and the desired base sampling frequency.
To utilize the maximum amount of DSP instructions, the core
clock should run at a rate of 1024 × f
S
.
Table 12. Clock Control Register (Register R0, Address 0x4000)
Bits Bit Name Settings
3 CLKSRC
0: Direct from MCLK pin (default)
1: PLL clock
[2:1] INFREQ[1:0]
00: 256 × f
S
(default)
01: 512 × f
S
10: 768 × f
S
11: 1024 × f
S
0 COREN
0: Core clock disabled (default)
1: Core clock enabled