Datasheet

ADAU1761
Rev. C | Page 15 of 92
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AGND
LINP
LINN
RINP
RINN
RAUX
ROUTP
ROUTN
SCL/CCLK SDA/COUT ADDR1/CDATA LRCLK/GPIO3 BCLK/GPIO2 DAC_SDATA/GPIO0 ADC_SDATA/GPIO1 DGND
PIN 1
INDICATOR
1IOVDD
2MCLK
3ADDR0/CLATCH
4JACKDET/MICIN
5MICBIAS
6LAUX
7CM
8AVDD
24 DVDDOUT
23 AVDD
22 AGND
21 MONOOUT
20 LHP
19 RHP
18 LOUTP
17 LOUTN
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
TOP VIEW
(Not to Scale)
ADAU1761
NOTES
1. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE
ADAU1761 GROUNDS. FOR INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE SOLDERED TO THE
GROUND PLANE.
07680-007
Figure 7. Pin Configuration
Table 10. Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
1 IOVDD PWR
Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD,
which also sets the highest input voltage that should be seen on the digital input pins.
IOVDD should be set between 1.8 V and 3.3 V. The current draw of this pin is variable because
it is dependent on the loads of the digital outputs. IOVDD should be decoupled to DGND
with a 100 nF capacitor and a 10 F capacitor.
2 MCLK D_IN External Master Clock Input.
3
ADDR0/CLATCH
D_IN I
2
C Address Bit 0 (ADDR0).
SPI Latch Signal (CLATCH
). Must go low at the beginning of an SPI transaction and high at the
end of a transaction. Each SPI transaction can take a different number of CCLKs to complete,
depending on the address and read/write bit that are sent at the beginning of the SPI
transaction.
4 JACKDET/MICIN D_IN Detect Insertion/Removal of Headphone Plug (JACKDET).
Digital Microphone Stereo Input (MICIN).
5 MICBIAS A_OUT Bias Voltage for Electret Microphone.
6 LAUX A_IN Left Channel Single-Ended Auxiliary Input. Biased at AVDD/2.
7 CM A_OUT
AVDD/2 V Common-Mode Reference. A 10 F to 47 F standard decoupling capacitor should
be connected between this pin and AGND to reduce crosstalk between the ADCs and DACs.
This pin can be used to bias external analog circuits, as long as they are not drawing current
from CM (for example, the noninverting input of an op amp).
8 AVDD PWR
1.8 V to 3.65 V Analog Supply for DAC and Microphone Bias. This pin should be decoupled
locally to AGND with a 100 nF capacitor.
9 AGND PWR
Analog Ground. The AGND and DGND pins can be tied together on a common ground plane.
AGND should be decoupled locally to AVDD with a 100 nF capacitor.
10 LINP A_IN Left Channel Noninverting Input or Single-Ended Input 0. Biased at AVDD/2.
11 LINN A_IN Left Channel Inverting Input or Single-Ended Input 1. Biased at AVDD/2.
12 RINP A_IN Right Channel Noninverting Input or Single-Ended Input 2. Biased at AVDD/2.
13 RINN A_IN Right Channel Inverting Input or Single-Ended Input 3. Biased at AVDD/2.
14 RAUX A_IN Right Channel Single-Ended Auxiliary Input. Biased at AVDD/2.
15 ROUTP A_OUT Right Line Output, Positive. Biased at AVDD/2.
16 ROUTN A_OUT Right Line Output, Negative. Biased at AVDD/2.
17 LOUTN A_OUT Left Line Output, Negative. Biased at AVDD/2.
18 LOUTP A_OUT Left Line Output, Positive. Biased at AVDD/2.