Datasheet

ADAU1761
Rev. C | Page 12 of 92
DIGITAL TIMING DIAGRAMS
BCLK
LRCLK
DAC_SDATA
LEFT-JUSTIFIED
MODE
LSB
DAC_SDATA
I
2
S MODE
DAC_SDATA
RIGHT-JUSTIFIED
MODE
t
BIH
MSB
MSB – 1
MSB
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
t
LIS
t
SIS
t
SIH
t
SIH
t
SIS
t
SIS
t
SIH
t
SIS
t
SIH
t
LIH
t
BIL
07680-002
Figure 2. Serial Input Port Timing
BCLK
LRCLK
ADC_SDATA
LEFT-JUSTIFIED
MODE
LSB
ADC_SDATA
I
2
S MODE
ADC_SDATA
RIGHT-JUSTIFIED
MODE
t
BIH
MSB
MSB – 1
MSB
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
t
SODM
t
BIL
07680-003
t
SODM
t
SODM
Figure 3. Serial Output Port Timing