Datasheet

ADAU1761
Rev. C | Page 11 of 92
DIGITAL TIMING SPECIFICATIONS
−40°C < T
A
< +85°C, IOVDD = 3.3 V ± 10%.
Table 7. Digital Timing
Limit
Parameter
t
MIN
t
MAX
Unit Description
MASTER CLOCK
t
MP
74 488 ns MCLK period, 256 × f
S
mode.
t
MP
37 244 ns MCLK period, 512 × f
S
mode.
t
MP
24.7 162.7 ns MCLK period, 768 × f
S
mode.
t
MP
18.5 122 ns MCLK period, 1024 × f
S
mode.
SERIAL PORT
t
BIL
5 ns BCLK pulse width low.
t
BIH
5 ns BCLK pulse width high.
t
LIS
5 ns LRCLK setup. Time to BCLK rising.
t
LIH
5 ns LRCLK hold. Time from BCLK rising.
t
SIS
5 ns DAC_SDATA setup. Time to BCLK rising.
t
SIH
5 ns DAC_SDATA hold. Time from BCLK rising.
t
SODM
50 ns ADC_SDATA delay. Time from BCLK falling in master mode.
SPI PORT
f
CCLK
10 MHz CCLK frequency.
t
CCPL
10 ns CCLK pulse width low.
t
CCPH
10 ns CCLK pulse width high.
t
CLS
5 ns
CLATCH
setup. Time to CCLK rising.
t
CLH
10 ns
CLATCH
hold. Time from CCLK rising.
t
CLPH
10 ns
CLATCH
pulse width high.
t
CDS
5 ns CDATA setup. Time to CCLK rising.
t
CDH
5 ns CDATA hold. Time from CCLK rising.
t
COD
50 ns
COUT three-stated. Time from CLATCH
rising.
I
2
C PORT
f
SCL
400 kHz SCL frequency.
t
SCLH
0.6 µs SCL high.
t
SCLL
1.3 µs SCL low.
t
SCS
0.6 µs Setup time; relevant for repeated start condition.
t
SCH
0.6 µs Hold time. After this period, the first clock is generated.
t
DS
100 ns Data setup time.
t
SCR
300 ns SCL rise time.
t
SCF
300 ns SCL fall time.
t
SDR
300 ns SDA rise time.
t
SDF
300 ns SDA fall time.
t
BFT
0.6 µs Bus-free time. Time between stop and start.
DIGITAL MICROPHONE R
LOAD
= 1 MΩ, C
LOAD
= 14 pF.
t
DCF
10 ns Digital microphone clock fall time.
t
DCR
10 ns Digital microphone clock rise time.
t
DDV
22 30 ns Digital microphone delay time for valid data.
t
DDH
0 12 ns Digital microphone delay time for data three-stated.