Datasheet

ADAU1701 Data Sheet
Rev. C | Page 8 of 52
Limit
Parameter t
MIN
t
MAX
Unit Test Conditions/Comments
MULTIPURPOSE PINS AND RESET
t
GRT
50 ns GPIO (MPx pins) rise time
t
GFT
50 ns GPIO (MPx pins) fall time
t
GIL
1.5 × 1/f
S
μs GPIO (MPx pins) input latency; time until high/low value is read by core
t
RLPW
20 ns
RESET
low pulse width
1
All timing specifications are given for the default (I
2
S) states of the serial input port and the serial output port (see Table 65).
Digital Timing Diagrams
INPUT_BCLK
INPUT_LRCLK
SDATA_INx
LEFT-JUSTIFIED
MODE
LSB
SDATA_INx
I
2
S MODE
SDATA_INx
RIGHT-JUSTIFIED
MODE
t
BIH
MSB
MSB – 1
MSB
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
t
LIS
t
SIS
t
SIH
t
SIH
t
SIS
t
SIS
t
SIH
t
SIS
t
SIH
t
LIH
t
BIL
0
6412-002
Figure 2. Serial Input Port Timing
CLATCH
CCLK
CDATA
COUT
t
CLS
t
CDS
t
CDH
t
COD
t
CCPH
t
CCPL
t
CLH
t
CLPH
06412-004
Figure 3. SPI Port Timing