Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- TABLE OF CONTENTS
- REVISION HISTORY
- FUNCTIONAL BLOCK DIAGRAM
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- TYPICAL PERFORMANCE CHARACTERISTICS
- SYSTEM BLOCK DIAGRAM
- THEORY OF OPERATION
- INITIALIZATION
- AUDIO ADCs
- AUDIO DACs
- CONTROL PORTS
- SIGNAL PROCESSING
- RAMS AND REGISTERS
- CONTROL REGISTER MAP
- CONTROL REGISTER DETAILS
- 2048 TO 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS
- 2056 (0x0808)—GPIO PIN SETTING REGISTER
- 2057 TO 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS
- 2064 TO 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS
- 2069 TO 2073 (0x0815 TO 0x819)—SAFELOAD ADDRESS REGISTERS
- 2074 TO 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS
- 2076 (0x081C)—DSP CORE CONTROL REGISTER
- 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER
- 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER
- 2080 TO 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS
- 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL
- 2084 (0x0824)—AUXILIARY ADC ENABLE
- 2086 (0x0826)—OSCILLATOR POWER-DOWN
- 2087 (0x0827)—DAC SETUP
- MULTIPURPOSE PINS
- LAYOUT RECOMMENDATIONS
- TYPICAL APPLICATION SCHEMATICS
- OUTLINE DIMENSIONS
Data Sheet ADAU1701
Rev. C | Page 7 of 52
REGULATOR
Table 6. Regulator
1
Parameter Min Typ Max Unit
DVDD Voltage
1.7
1.8
1.84
V
1
Regulator specifications are calculated using a Zetex Semiconductors FZT953 transistor in the circuit.
DIGITAL TIMING SPECIFICATIONS
Table 7. Digital Timing
1
Limit
Parameter t
MIN
t
MAX
Unit Test Conditions/Comments
MASTER CLOCK
t
MP
36 244 ns MCLKI period, 512 × f
S
mode
48 366 ns MCLKI period, 384 × f
S
mode
73 488 ns MCLKI period, 256 × f
S
mode
291 1953 ns MCLKI period, 64 × f
S
mode
SERIAL PORT
t
BIL
40 ns INPUT_BCLK (Pin 9) low pulse width
t
BIH
40 ns INPUT_BCLK (Pin 9) high pulse width
t
LIS
10
ns
INPUT_LRCLK (Pin 8) setup; time to INPUT_BCLK rising
t
LIH
10 ns INPUT_LRCLK (Pin 8) hold; time from INPUT_BCLK rising
t
SIS
10 ns
SDATA_INx (Pin 10, Pin 11, Pin 28, or Pin 29) setup; time to INPUT_BCLK (Pin 9)
rising
t
SIH
10 ns
SDATA_INx (Pin 10, Pin 11, Pin 28, or Pin 29) hold; time from INPUT_BCLK (Pin 9)
rising
t
LOS
10 ns OUTPUT_LRCLK (Pin 16) setup in slave mode
t
LOH
10 ns OUTPUT_LRCLK (Pin 16) hold in slave mode
t
TS
5 ns OUTPUT_BCLK (Pin 11) falling to OUTPUT_LRCLK (Pin 16) timing skew
t
SODS
40 ns SDATA_OU Tx (Pin 14, Pin 15, Pin 26, or Pin 27) delay in slave mode; time from
OUTPUT_BCLK (Pin 11) falling
t
SODM
40 ns SDATA_OUTx (Pin 14, Pin 15, Pin 26, or Pin 27) delay in master mode; time from
OUTPUT_BCLK (Pin 11) falling
SPI PORT
f
CCLK
6.25 MHz CCLK (Pin 23) frequency
t
CCPL
80 ns CCLK (Pin 23) pulse width low
t
CCPH
80 ns CCLK (Pin 23) pulse width high
t
CLS
0 ns CLATCH (Pin 21) setup; time to CCLK (Pin 23) rising
t
CLH
100 ns CLATCH (Pin 21) hold; time from CCLK (Pin 23) rising
t
CLPH
80 ns CLATCH (Pin 21) pulse width high
t
CDS
0
ns
CDATA (Pin 20) setup; time to CCLK (Pin 23) rising
t
CDH
80 ns CDATA (Pin 20) hold; time from CCLK (Pin 23) rising
t
COD
101 ns COUT (Pin 22) delay; time from CCLK (Pin 23) falling
I
2
C PORT
f
SCL
400 kHz SCL (Pin 23) frequency
t
SCLH
0.6 µs SCL (Pin 23) high
t
SCLL
1.3 µs SCL (Pin 23) low
t
SCS
0.6 µs Setup time, relevant for repeated start condition
t
SCH
0.6 µs Hold time; after this period, the first clock is generated
t
DS
100 ns Data setup time
t
SCR
300 ns SCL (Pin 23) rise time
t
SCF
300 ns SCL (Pin 23) fall time
t
SDR
300 ns SDA (Pin 22) rise time
t
SDF
300 ns SDA (Pin 22) fall time
t
BFT
0.6
Bus-free time; time between stop and start