Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- TABLE OF CONTENTS
- REVISION HISTORY
- FUNCTIONAL BLOCK DIAGRAM
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- TYPICAL PERFORMANCE CHARACTERISTICS
- SYSTEM BLOCK DIAGRAM
- THEORY OF OPERATION
- INITIALIZATION
- AUDIO ADCs
- AUDIO DACs
- CONTROL PORTS
- SIGNAL PROCESSING
- RAMS AND REGISTERS
- CONTROL REGISTER MAP
- CONTROL REGISTER DETAILS
- 2048 TO 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS
- 2056 (0x0808)—GPIO PIN SETTING REGISTER
- 2057 TO 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS
- 2064 TO 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS
- 2069 TO 2073 (0x0815 TO 0x819)—SAFELOAD ADDRESS REGISTERS
- 2074 TO 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS
- 2076 (0x081C)—DSP CORE CONTROL REGISTER
- 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER
- 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER
- 2080 TO 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS
- 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL
- 2084 (0x0824)—AUXILIARY ADC ENABLE
- 2086 (0x0826)—OSCILLATOR POWER-DOWN
- 2087 (0x0827)—DAC SETUP
- MULTIPURPOSE PINS
- LAYOUT RECOMMENDATIONS
- TYPICAL APPLICATION SCHEMATICS
- OUTLINE DIMENSIONS
Data Sheet ADAU1701
Rev. C | Page 47 of 52
LRCL
K
BCLK
SDATA MSB
LEFT CHANNEL
LSB
MSB
RIGHT CHANNEL
LSB
1/F
S
06412-031
Figure 32. I
2
S Mode—16 Bits to 24 Bits per Channel
LRCLK
BCLK
SDATA
LEFT CHANNEL
MSB LSB
MSB
RIGHT CHANNEL
LSB
1/F
S
0
6412-032
Figure 33. Left-Justified Mode—16 Bits to 24 Bits per Channel
LRCLK
BCLK
SDATA
LEFT CHANNEL
MSB LSB MSB
RIGHT CHANNEL
LSB
1/F
S
06412-033
Figure 34. Right-Justified Mode—16 Bits to 24 Bits per Channel
LRCLK
BCLK
DATA
SLOT 1 SLOT 4 SLOT 5
32 BCLKs
MSB MSB–1 MSB–2
256 BCLKs
SLOT 2 SLOT 3 SLOT 6 SLOT 7 SLOT 8
LRCLK
BCLK
DATA
06412-034
Figure 35. TDM Mode
LRCL
K
SLOT 0 SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7
CH
0
BCLK
SDATA
MSB TDM
8TH
CH
32
BCLKs
MSB TDM
06412-035
Figure 36. TDM Mode with Pulse Word Clock