Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- TABLE OF CONTENTS
- REVISION HISTORY
- FUNCTIONAL BLOCK DIAGRAM
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- TYPICAL PERFORMANCE CHARACTERISTICS
- SYSTEM BLOCK DIAGRAM
- THEORY OF OPERATION
- INITIALIZATION
- AUDIO ADCs
- AUDIO DACs
- CONTROL PORTS
- SIGNAL PROCESSING
- RAMS AND REGISTERS
- CONTROL REGISTER MAP
- CONTROL REGISTER DETAILS
- 2048 TO 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS
- 2056 (0x0808)—GPIO PIN SETTING REGISTER
- 2057 TO 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS
- 2064 TO 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS
- 2069 TO 2073 (0x0815 TO 0x819)—SAFELOAD ADDRESS REGISTERS
- 2074 TO 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS
- 2076 (0x081C)—DSP CORE CONTROL REGISTER
- 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER
- 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER
- 2080 TO 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS
- 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL
- 2084 (0x0824)—AUXILIARY ADC ENABLE
- 2086 (0x0826)—OSCILLATOR POWER-DOWN
- 2087 (0x0827)—DAC SETUP
- MULTIPURPOSE PINS
- LAYOUT RECOMMENDATIONS
- TYPICAL APPLICATION SCHEMATICS
- OUTLINE DIMENSIONS
ADAU1701 Data Sheet
Rev. C | Page 4 of 52
FUNCTIONAL BLOCK DIAGRAM
2
2
GPIO
INPUT/OUTPUT MATRIX
DIGITAL
VDD
DIGITAL
GROUND
ANALOG
VDD
ANALOG
GROUND
PLL
MODE
PLL LOOP
FILTER
CRYSTAL
3.3V
28-/56-BIT, 50MIPS
AUDIO PROCESSOR CORE
40ms DELAY MEMORY
2-CHANNEL
ANALOG
INPUT
1.8V
REGULATOR
STEREO
ADC
FILTA/
ADC_RES
RESET/
MODE
SELECT
CONTROL
INTERFACE
AND
SELFBOOT
8-CH
DIGITAL
INPUT
8-CH
DIGITAL
OUTPUT
8-BIT
AUX
ADC
RESET
SELFBOOT
DIGITAL IN
OR GPIO
AUX ADC
OR GPIO
DIGITAL OUT
OR GPIO
I
2
C/SPI
AND WRITEBACK
DAC
DAC
4-CHANNEL
ANALOG
OUTPUT
FILTD/CM
PLL
CLOCK
OSCILLATOR
ADAU1701
3
3
3
2
2
2
3
3
3
5
06412-001
Figure 1.