Datasheet

Data Sheet ADAU1701
Rev. C | Page 31 of 52
Table 21. Parameter RAM Read/Write Format (Single Address)
Byte 0 Byte 1 Byte 2 Byte 3 Bytes[4:6]
chip_adr[6:0],
W
/R
000000, param_adr[9:8] param_adr[7:0] 0000, param[27:24] param[23:0]
Table 22. Parameter RAM Block Read/Write Format (Burst Mode)
Byte 0 Byte 1 Byte 2 Byte 3 Bytes[4:6] Bytes[7:10] Bytes[11:14]
chip_adr[6:0],
W
/R 000000, param_adr[9:8] param_adr[7:0] 0000, param[27:24] param[23:0]
<—param_adr—> param_adr + 1 param_adr + 2
Table 23. Program RAM Read/Write Format (Single Address)
Byte 0
Byte 1
Byte 2
Bytes[3:7]
chip_adr[6:0],
W
/R
00000, prog_adr[10:8] prog_adr[7:0] prog[39:0]
Table 24. Program RAM Block Read/Write Format (Burst Mode)
Byte 0 Byte 1 Byte 2 Bytes[3:7] Bytes[8:12] Bytes[13:17]
chip_adr[6:0],
W
/R
00000, prog_adr[10:8]
prog_adr[7:0]
prog[39:0]
<—prog_adr—> prog_adr + 1 prog_adr + 2
Table 25. Control Register Read/Write Format (Core, Serial Out 0, Serial Out 1)
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
chip_adr[6:0],
W
/R
0000, reg_adr[11:8] reg_adr[7:0] data[15:8] data[7:0]
Table 26. Control Register Read/Write Format (RAM Configuration, Serial Input)
Byte 0 Byte 1 Byte 2 Byte 3
chip_adr[6:0],
W
/R
0000, reg_adr[11:8] reg_adr[7:0] data[7:0]
Table 27. Data Capture Register Write Format
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
chip_adr[6:0],
W
/R
0000, data_capture_adr[11:8] data_capture_adr[7:0] 000, progCount[10:6]
1
progCount[5:0]
1
, regSel[1:0]
2
1
progCount[10:0] is the value of the program counter when the data capture occurs (the table of values is generated by the SigmaStudio compiler).
2
regSel[1:0] selects one of four registers (see the 2074 to 2075 (0X081A to 0X081B)—Data Capture Registers section).
Table 28. Data Capture (Control Port Readback) Register Read Format
Byte 0 Byte 1 Byte 2 Bytes[3:5]
chip_adr[6:0],
W
/R 0000, data_capture_adr[11:8] data_capture_adr[7:0] data[23:0]
Table 29. Safeload Address Register Write Format
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
chip_adr[6:0],
W
/R
0000, safeload_adr[11:8]
safeload_adr[7:0]
000000, param_adr[9:8]
param_adr[7:0]
Table 30. Safeload Data Register Write Format
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Bytes[5:7]
chip_adr[6:0],
W
/R 0000, safeload_adr[11:8] safeload_adr[7:0] 00000000 0000, data[27:24] data[23:0]