Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- TABLE OF CONTENTS
- REVISION HISTORY
- FUNCTIONAL BLOCK DIAGRAM
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- TYPICAL PERFORMANCE CHARACTERISTICS
- SYSTEM BLOCK DIAGRAM
- THEORY OF OPERATION
- INITIALIZATION
- AUDIO ADCs
- AUDIO DACs
- CONTROL PORTS
- SIGNAL PROCESSING
- RAMS AND REGISTERS
- CONTROL REGISTER MAP
- CONTROL REGISTER DETAILS
- 2048 TO 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS
- 2056 (0x0808)—GPIO PIN SETTING REGISTER
- 2057 TO 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS
- 2064 TO 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS
- 2069 TO 2073 (0x0815 TO 0x819)—SAFELOAD ADDRESS REGISTERS
- 2074 TO 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS
- 2076 (0x081C)—DSP CORE CONTROL REGISTER
- 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER
- 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER
- 2080 TO 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS
- 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL
- 2084 (0x0824)—AUXILIARY ADC ENABLE
- 2086 (0x0826)—OSCILLATOR POWER-DOWN
- 2087 (0x0827)—DAC SETUP
- MULTIPURPOSE PINS
- LAYOUT RECOMMENDATIONS
- TYPICAL APPLICATION SCHEMATICS
- OUTLINE DIMENSIONS
ADAU1701 Data Sheet
Rev. C | Page 28 of 52
The writeback function writes data from the ADAU1701
interface registers to the second page of the self-boot EEPROM,
Address 32 to Address 63. Starting at EEPROM Address 26
(so that the interface register data begins at Address 32), the
EEPROM should be programmed with six bytes—the message
byte (0x01), two length bytes, the chip address (0x00), and the
2-byte subaddress for the interface registers (0x08 0x00). There
must be a message to the DSP core control register to enable
writing to the interface registers prior to the interface register
data in the EEPROM. This should be stored in EEPROM
Address 0. No-op messages (0x03) can be used in between
messages to ensure that these conditions are met.
The ADAU1701 writes to EEPROM Chip Address 0xA0. The
LSBs of the addresses of some EEPROMs are pin configurable; in
most cases, these pins should be tied low to set the address to 0xA0.
The maximum number of bytes that is written back from the
ADAU1701 is 35 (eight 4-byte interface registers plus three
bytes of EEPROM-addressing overhead). With SCL running at
384 kHz, the writeback operation takes approximately 73 μs to
complete after being triggered. Ensure that sufficient power is
available to the system to allow enough time for a writeback to
complete, especially if the WB signal is triggered from a falling
power supply voltage.
Table 19. EEPROM Message Types
Message ID Message Type Following Bytes
0x00 End None
0x01 Write
Two bytes indicating message length followed by appropriate
number of data bytes
0x02 Delay Two bytes for delay
0x03 No operation executed None
0x04 Set multiple writeback None
0x05 Set WB to falling edge sensitive None
0x06 End and wait for writeback None
0x01 0x00 0x05 0x00 0x08 0x1C 0x00 0x40
WRITE LENGTH DEVICE
ADDRESS
CORE CONTROL REGISTER
ADDRESS
CORE CONTROL REGISTER
DATA
0x01 0x001 0x61 0x00 0x04 0x00 0x00 0x00
WRITE LENGTH DEVICE
ADDRESS
PROGRAM RAM ADDRESS PROGRAM RAM DATA
0x00 0x00 0x01 0x00 0x00 0x00 0xE8 0x01
PROGRAM RAM DATA
0x00 0x00 0x00 0x00 0x01 0x00 0x08 0x00
PROGRAM RAM DATA (CONTINUES FOR 332 MORE BYTES)
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
INTERFACE REGISTER DATA
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
INTERFACE REGISTER DATA
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
INTERFACE REGISTER DATA
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
INTERFACE REGISTER DATA
0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03
NO-OP BYTES
0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03
NO-OP BYTES
0x03 0x03 0x01 0x00 0x23 0x00 0x08 0x00
LENGTH DEVICE
ADDRESS
INTERFACE REGISTER
ADDRESS
WRITENO-OP BYTES
06412-039
Figure 28. EEPROM Data Example